Removing spikes from low-voltage supply voltage in a dc-dc converter 5

[bpelec]

I have designed and built a 2 kW, full-bridge, dc-dc converter.

As part of this conveter, I have a double-sided PCB board that contains the control/driver circuitry and the four power switches. I have three separate copper pours that each create a local ground plane for the control circuitry, the drivers and the MOSFETs respectively. These three ground planes are connected together at a single point, where the power enters the board. I have three separate power tracks that run to each of these three areas to provide the dc voltages. The dc voltages for the control and drivers is 15v dc, and the dc voltage that goes to the MOSFETs is around 340v dc.

I have added an electrolytic capacitor (47uF-100uF) in parallel with a ceramic capacitor (0.1uF) between each of the three ground and power tracks that go to each area of the board, just after the tracks leave the single connection point where the power enters the board.

I thought that I had therefore put together a pretty good design in terms of removing noise and spikes from my low-voltage dc supply tracks. I do also have local decoupling of all the chips using a ceramic capacitor next to the chips.

However, when I turn on my system which is switching several amps at 100 kHz, I get some really unpleasant spikes on the 15 dc supply tracks at around 7-10 Mhz, relative to the local grounds... I would have expected my electrolytic/cermanic capacitor combo to sort out the problem...

So, I guess where I am going wrong is in my choice of capacitors, both in terms of value and ESR....

My question is this... If I wanted to formally work out what decoupling capacitors to use to remove/reduce the spikes on my low-voltage dc-spply, how should I do it?

Thanks in advance.

Best regards,

BPELEC.

 

[itsmoked]

Caps here, are extremely critical as there are large pulses of current being moved here and there. The current spikes are large enough that the meager inductance in the traces and pins of the devices amount to a large enough chunk of stored energy, that when it returns as voltage, when the gate is shutting off, it's a large spike. You haven't stated whether you are in SMT or thru-hole land.

Caps need to be low ESR type (typically ESR<0.5 Ohms).

Leads must be very short(SMD superior) and must be very close to the switching elements.

Aluminum caps typically have high ESR. Tantalum's are superior in this regard and the new large value ceramics are even better. Leaded devices.. not as good as the leads are inductors which cancel the caps effectiveness.

Keith Cress
Flamin Systems, Inc.-

http://www.flaminsystems.com

 

[Skogsgurra]

bpelec,

You are saying: "I have added an electrolytic capacitor (47uF-100uF) in parallel with a ceramic capacitor (0.1uF)...just after the tracks leave the single connection point where the power enters the board."

That would mean that you filter the rails where there is not much to filter (the tracks are as close to short-circuited as they can be at the point of common coupling). So your capacitors will not help much. Try to put the capacitors where your problem is instead.

A couple of questions: Does the noise cause any problems? Are you sure that the noise is real? (Many times an improper probe ground connection can make things look worse than they actually are).




Gunnar Englund

http://www.gke.org

 

[bpelec]

Thank you both for your input.

skogsgurra, my thinking was that by placing the capacitors at that point, and with the ground-planes being separate after that point, I would prevent the inevitable spikes on the MOSFET's ground plane coupling to the low-voltage dc planes... Does that thinking make sense?

To answer your other questions... I started to investigate the spikes after one of my chips died twice during turn on. My initial thoughts were that a large spike was occassionally ocurring when I turned on the system. To help prevent that I have order some transient voltage suppressors (Transil/Transorb) in order to protect my low-voltage circuitry. However, I then found that I had constant spikes due to the switching all the time. These spikes exceed the maximum voltage for the chip that keeps blowing. I am measuring these voltage using a battery powered differential probe between the points in question, so I don't think I have grounding problems with the probe.

Best regards,

BPELEC.

 

[bpelec]

Just to clarify, the chip was failing by forming a short across the low-voltage dc power supply and drawing a very large current. This is why I started to investigae this power supply.

 

[MacGyverS2000]

You'll have to scope it out yourself and decide, but I try to stay away from jumping more than an order of magnitude when combining caps. You have 0.1uF and 100uF, but nothing in the 1uF and 10uF range. They may not be necessary, but depending upon your track resistance/inductance, you could be missing a large range of frequency attentuation by not including them.

Dan - Owner

http://www.Hi-TecDesigns.com

 

[IRstuff]

Seems to me that you have two potentially separate problems.

Firstly, where are these spikes coming from? They're up to 100 times higher than your switching frequency. Are they a natural fallout of your circuit, or is something else wrong?

What kind chip died? Was it connected to I/O? If so, are there some separations between its ground and whatever it was driving/receiving? 422 receivers cannot take much in the way of common mode. If the source and receiver at driven by different supplies, their power-on transients may differ enough to cause a huge common-mode and their respective grounds need to be bridged somehow.

TTFN

 

[itsmoked]

We could offer you FAR better assitance with a schematic, and in your case, a clear picture of the board, since a whole lot of your problem could be layout.

See faq238-1161

Keith Cress
Flamin Systems, Inc.-

http://www.flaminsystems.com

 

[bpelec]

macgyvers2000, that's a good point. I think I do need to work out the specific frequency ranges I need to filter and take this into account when choosing the capacitance and ESR of the decoupling capacitors.

IRstuff, I think the spikes are caused by the fast rising switching of the MOSFETS. To claify, the spikes occur in line with the switching transitions of the MOSFETS. The spikes themselves have a frequency of about 7-10 Mhz.

itsmoked, I was thinking along the same lines... I will post my circuit schematic and my PCB layout in the next couple of days.

Thank you for all your help and I will return with more info.

Best regards,

BPELEC.

 

[bpelec]

Here is a link to a picture of the schematic:

http://files.bpotter.jetemail.net/public/schematic.jpg

Here is a link to a picture of the PCB layourt:

http://files.bpotter.jetemail.net/public/PCB_layout2.jpg

It would probably be best to download the pictures and open them in a program with a zoom feature. I have annotated the PCB layout.

Let me know if any of it doesn't make sense and I will do my best to explain...

Best regards,

BPELEC.

 

[Skogsgurra]

I would be very reluctant to have an IC straddling two ground planes that are not solidly connected. The idea to have two different ground planes may seem just right. But my bet is that your problem is there. Connect the two with broad traces (or just pour copper between them).

You have presented a clean and easy-to-understand diagram, but I have not been able to see where on the PCB you have put the capacitors. Could you indicate with some more text where they are?

Gunnar Englund

http://www.gke.org

 

[benta]

I agree with Gunnar, the layout is not optimal, and having two sides of an IC on different planes is not good.
I think you need to rethink and analyse where the ground "bounces". Basically, that's on the blue trace from the power connector down to the MOSFETs. This means that they are moving (ground-wise) with respect to your driver circuit. Not nice at all.
I would do the following:
1: place the whole control section on one ground plane.
2: connect this GP to the middle of the ground between the MOSFETs (going through the "IR2113 Driver" text).
This way your reference point is stable with respect to potential differences between power stage and control section. The whole circuit bounces a bit due to current through the thick blue trace, but this shouldn't be a big issue.
On a related note, I'm a bit surprised that you don't go for optical drive on a converter this size, that solves a lot of problems.

Benta.

 

[bpelec]

Thanks skogsgurra. Here is an updated version of the PCB layout showing the location of the capacitors:

http://files.bpotter.jetemail.net/public/PCB_layout3.jpg

You may well be right about that chip straddling the ground planes, and I will look into it... However, that chip (UCC 2895) has two separate ground pins, one for the clock side and one for the output side... Those grounds do need to be connected together at some point, but my thinking was that it would be best to do that at the supply.

If I connect those two ground planes together right now, I would create a ground loop as they are currently tied together at the supply. I guess I could just cut the track that goes back to the supply.

Thanks,

BPELEC.

 

[bpelec]

I guess the main reason why I went for this kind of design was because I thought that I had to meet two requirements:

1) Use thick, direct tracks to connect components to the power rail and ground, and keep these two tracks very close together. Go for a star point ground connection.

2) Don't just have one huge copper pour over everything. Based upon 1, sometimes it is better to avoid ground plances altogether. If there were no ground planes, the you'd just have the tracks and they would be connected to a star point ground.

Benta, I suppose my thinking was that by having my capacitors on separte ground paths, the inevitable ground bounce near the MOSFETs could not get to the control circuitry, as it would have to get through four capacitors. Is this where my thinking is flawed?

I needed the IR2113 drivers in order to provide sufficient current to turn on the MOSEFTs as I wished. I could have opted for opto-isolators between the control chip and the IR2113s, but I was worried about bandwidth and I thought my ground strategy would be sufficient. Also, the ground of the control circuitry, even including opto-isolators would ultimately have to be connected to the same ground as the DC link for the MOSFETs wouldn't it...

Hmm, lots to think about. I am very grateful for all your time and help.

Best regards,

BPELEC.

 

[cbarn24050]

http://www.irf.com/technical-info/designtp/dt04-4.pdf

 

[MacGyverS2000]

I see a number of issues with the current layout. Personally, I've never been a fan of connecting multiple ground planes at points far away from the actual plane... it leads to antennas that can radiate and/or pick up high-frequency clutter. Your traces also wander unnecessarily... upper left connector, the far left blue trace goes down-right, down, then down-left... no reason for it not to just go straight down (at least that I can see without a schematic/parts placement diagram). Your FETs could also be placed closer to the driver chip. Unless you have a specific reason to separate ground at a particular point (and in this circuit there are a few places that holds true), go ahead and make the ground planes as wide as possible wherever possible... good for heatsinking and prevents odd spots, like near the top right where the ground plane snakes up and right before finally coming down to the FETs.


Dan - Owner

http://www.Hi-TecDesigns.com

 

[bpelec]

Thank you macgyvers2000. In your post, you mention that in my design there are a few points where I would not want to connect the ground together... In your opinion, where would these points be?

Thanks again everyone! I am learning a lot from all of your post. I haven't had a good humbling moment for a while, and I reckon it has certainly been due!..

Best regards,

BPELEC.