Using Flowtherm to find junction temp. 4

[Twoballcane]

Hi guys
Has anybody used flowtherm to find junction temp. of FPGA and such?

Thanks in advance for any advice.

 

[ko99]

Yes, many times. What do you want to know?

ko (

http://www.ecooling.biz)

 

[Twoballcane]

Thanks for responding ko99

I am just learning flowtherm, I uasally use TAS to find junction temps, but for flowtherm how would you usally go about setting up the model. If I had to find the junction temp of a FPGA that is soldered down to a thermal pad with thermal vias...how would you do that? Off the top of my head I would use a cuboid (in PCB assembly) for the FPGA, use a collapsed cuboid for the solder, and then use cuboids for the board and thermal vias. To find the junction temp I would put a monitoring point in the FPGA. would this sound right to you?

Thank you for your time
Twoballcane

 

[IRstuff]

no, you would need to correctly model the die within the FPGA package to accurately model the junction temperature

TTFN

 

[Twoballcane]

Hi irstuff,
Well if i know the theta junction to case already then I don't have to do that. In TAS I usally just find the case temp and then calc the junction temp from there...

 

[Twoballcane]

sorry irstuff now that I'm thinking about it that sounds like a good idea to creat another cuboid within the cuboid that reresents the FPGA. Is that the way you use flowtherm?

 

[IRstuff]

I don't personally use Flotherm, but if you've got the data to input, then that somewhat reasonable.

However, I think you'd still need to get the die, e.g., the actual heat source in the right place in the package with the right thermal spreading resistance to get the correct match to the conditions used to derive or calculate the theta.jc, since I assume that you need to place a heat source somewhere inside your cuboid to make the analysis work correctly.

Depending on the manufacturer and the power dissipation, the actual geometry of the die/package can be quite different.

TTFN

 

[ko99]

There are many ways to model an IC package in Flotherm, from fully detailed to general compact model to 2-resistor model to a simple block, and various combinations of these.

For your application, I suggest a detailed or general compact model. It's easiest to generate these with Flopack, but if you don't have this option you can use the "compact component" in the geometry pallette or try the method described here:

http://www.flomerics.com/flotherm/support/supp/advtopics/modelbga/

(you may need to be a registered user to access this file...)

Also, instead of simple blocks for the PCB, you can use "PCB" in the geometry pallette and enter the copper content and thickness at each layer. You can then superimpose any local vias over this as blocks with orthotropc conduction.




ko (

http://www.ecooling.biz)

 

[tkordyban]

The Theta j-c that is published in component data sheets is generally not an accurate value for the thermal resistance between the juction and the BOTTOM side of the package. You mention a solder pad on the bottom of the package. Theta j-c is usually measured as the thermal resistance between the die and the TOP side of the package. Unless all the sides of the package are the same temperature, which is highly unlikely in a package design like the one you describe, then Theta j-c is not a good value to use for estimated junction temperature from the case temperature on the bottom of the package.

I recommend FLOPACK for getting a detailed model of the package, or, even better, ask the component vendor to tell you the value of Theta j-b, the thermal resistance between the junction and the board. Sometimes they know that value, especially if the package is designed to have a good thermal path into the board through a solder pad.

Good luck with that. Your question is the most common in thermal analysis of electronic components, and there is no good easy answer to it yet.

 

[ko99]

Good point. If it's available, a manufacturer's Theta j-b with a 2-resistor model is the easiest way to model the FPGA. Just be aware that results are sensitive to the contact area between the component and the pcb.

For example, a BGA with solder balls only around the periphery won't make contact with the pcb pad and vias under the center of the package, but a 2-resistor model does make contact here and may give misleading results.

ko (

http://www.ecooling.biz)

 

[Twoballcane]

thank you guys for your time!