Sample and Hold problems

[courtl]

Hi there,

I am currently having a problem with a Sample and Hold circuit that is used to Sample a voltage which can range from 3V down to 2mV. The output of this is then fed to a comparator which compares the sample and hold value with the next signal received. This then either gives an output to a PLD to show a pass or a fail.

The threshold levels for the comparator are set using SOT vlaue resistors from a +15V and -15V supply.

However I have the problem that some IC's of the same batch will not allow the threshold levels to be set, while others will i.e the comparator will never output a fail but some do. I have an external hold cap to control the droop rate.

I was wondering whether this was due to the fact that some of the IC's may be more sensitive to the very low levels of ample voltage i.e. 2mV where it should cause a fail.

The problem is I have looked very closely at the input and output from the Sample and hold and can see no difference in performance between those that work and those that don't.

Sorry this is a bit of a waffle, but if anyone has any suggestions they would be gratefully received as I have very limited knowledge of Sample and Hold circuits.

Many Thanks

 

[BrianG]

Here's some points to ponder:

You don't say what your S/H chip is actually sampling - is it a pulse, or d.c., or what?

Is the sample gate signal wide enough for this application and occuring at the right time?

2mV is relatively small - do the very low levels have any noise superimposed on them? (Digital/Analog grounding layout problems.)

Does your deisgn take into account different input offset voltages of individual comparator chips?

Is your reference level potential divider of low enough impedance not to shift around with different comparator chip input bias current variations?

 

[automatic2]

What is the tolerance/quality of your hold capacitor?. Use of electroyitc for hold would be a problem.

 

[courtl]

Thanks for the suggestions BrianG and automatic2. The S/H is sampling part of a pulse. The Sample gate signal is coming from a PLD and is definately wide enough for this application.

The offset and noise is something I have thought about when we are sampling down at 2mV, there is a small amount of noise but nothing unexpected. Do you have any suggestions on how to look for offsets.

I have done numerous measurements on 'good' S/H against 'bad' S/H's but can see no obvious differences in the signals going in or out, or points around the comparator.

The capacitor I am using is a ceramic, I have read recently that ceramics and electrolytics suffer from absorbsion errors in this kind of application, however I have tried using the recommended polypropylene type and this made no improvement.

 

[BrianG]

If I have understood you correctly your comparator is trying to detect signals greater than about 2mV as a "pass" and less than 2mV as a "fail"?

If so, then the reference voltage for the comparator is around 2mV, but if this is derived from +/- 15V supply rails it will require very close tolerance, low noise resistors with excellent temp coeffs. What about supply rail changes or noise, and have you decoupled the reference voltage?
(I would personally design this sort of circuit using a band-gap precision reference device and then the resistive dividers.)

However, if you are using SOT resistors why can't you just "tune" each comparator as needed to get a pass/fail at the right voltage levels? This would eliminate any small input offset voltage variation problem.

 

[electricuwe]

Different leakage currents of the S/H chips might be the source of the problem. Leakage currents usually show much larger variations that offset voltages. Check what voltage change a leakage current of the S/C chip would cause if it is at it's upper specified limit and the hold time is at maximum.