Circuit board pad layout.

[mosfit]

What are the possible manufacturing issues and drawbacks involved in using a pad layout that is exactly the same dimensions as the maximum tolerance of the footprint of the device being installed? Can I get away with having a 7% overhang of the interior "heel" of the surface mount part relative to the pad?  Why should I follow an IPC recomended pad layout that takes up so much of my board space when the device will fit snug on a smaller layout?

 

[RolandP]

In the case of a gull wing device (pqfp and tsop)
most if not all of the strength of the solder holding
the part to the board comes from the heel of the joint.
The side filet and toe filet contribute very little
to the strength. There are good reasons for the
recommended pad sizes. Only experience will tell you
when it is too conservative. The IPC-A-610 Acceptability
of Electronic Assemblies is a good place to learn what is and what is not a good solder joint. Read and re-read chapter 12.

The IPC strongly recommendeds that you read the philosophy of land pattern design in the IPC-SM-782A Surface Mount Design and Land Pattern Standard.

The IPC also has a land pattern calculator.

http://www.ipc.org/html/fsresources.htm

Good luck.

Roland