Back to back FETs

[MacGyverS2000]

Can anyone think of issues I might encounter by putting MOSFETs back to back (D to S, and S to D, G and G tied together), like an AC switch? When the gate is enabled, I want a signal to pass through this "switch", regardless of which end has the higher potential. I didn't think a single MOSFET would accomplish the goal due to the varying potentials.

As always, replacement circuit suggestions welcome (I'm using SOT-23 packages, so any replacement must be compact).

 

[MacGyverS2000]

Same voltage (5V) on both sides, I just mentioned the bus level translators as they would do what I wanted if 5V was provided as the supply for both sides... couldn't find any other transceiver style of component other than bus translators.

I also considered the back to back buffer idea, but couldn't get past they thought of them getting into a race condition of some sort. Connecting the output of buffer 1 to the enable of buffer 2 (and vice versa) seems fine on paper, but real-world components might not like that idea as much. Not to mention one buffer will try to keep the line low/high while a processor down the line tries to drag it in the other direction. Or am I missing the obvious?

 

[felixc]

I'm missing something. An LVXC4245 would be fine if it was working at 5 volts on both sides? Then why just a regular 245 bidirectional driver can't do the job?

Output of buffer 1 to enable of buffer 2? what do you mean?

Take a look at NC7WZ241. I think it does exactly what you're looking for. If not please explain differently what you're trying to do.

 

[MacGyverS2000]

Yes, the LVCX4245 would work fine for this app, if it was significantly smaller... it's an 8-bit transceiver, but I only need 1 channel (I'll accept 2 channel, as the package would probably still be relatively small).

I'm definitely missing the hookup of a dual buffer with output enable, then. Since this is a single wire transmission, the output of buffer 1 needs to hook to the input of buffer 2, and vice versa. Like this:

    |--|
    |  |
    |  |\
----|--| >---|-----
    |  |/    |
    |        |
    |        |
    |   /|   |
    |--< |---|
        \|   |
         |   |
         |---|

At logic 0, we're fine, as both buffers are in a high-impedance state. When a logic 1 (5V) comes down the line, weimmediately run into a snag... a processor will be trying to drive the line high, but so will the opposing buffer. If a 0 is transmitted again, the buffers will continue to drive the line high indefinitely.

The dual active-high/active-low enable operation of the NC7WZ241 doesn't help resolve the issue. A logic 1 will never get through the active-low buffer, and a logic 0 will never make it through the active-high buffer.

Honestly, I'm quite interested in how they make minimal size transceivers (SOT-23) with a minimum of logic gates... seems tricky.

 

[felixc]

I don't get it. The data controls the tri-state oputput as well?

 

[MacGyverS2000]

I don't want it to, but in that configuration it does. I will remove power from the buffers altogether when they're not needed, but otherwise they should be powered and doing their job. It's a two-way communication line that I would like to ensure has enough power... I do not yet know if the edges will need periodic sharpening, so a schmitt trigger input to the buffers is ideal.

 

[cbarn24050]

Hi, check out SN74LVC1T45.

 

[MacGyverS2000]

At first thought, back to back buffers seems the way to go. Further thought says the input of one needs to tri-state the output of the other. Even further says that just won't work. I was going to post a small mass of gates necessary to make this work, then decided by the time I go through with all of that, the circuit would be quite large.

Luckily enough, this circuit will not need to be used very often, so I can skip populating those pieces on the boards that won't need it. That being the case, I'm leaning towards two possible solutions.

1) A small processor, like a PIC 12F series, with interrupt-on-change capability. It may introduce a minor delay in the signal, but if coded correctly, the delay should be constant. I would have complete control over both sides of the bus, and although I probably wouldn't have Schmitt trigger inputs, the output signals would have sharp edges again. With oscillator and support components, the circuit should be less than $2. Board space should be around 0.5" square, even less if I use both sides of the board (the oscillator will be larger than the processor ;-) ).

2) A small PLD or the like with a setup similar to the above. I don't know if they make PLDs as small (or as cheap) as the PIC mentioned above, but it's worth a shot to look for one. I would need to purchase more programming equipment (that stinks), but there is potential for the unit to be really cheap (only potential, as the cheapest PIC is $0.55!).




I hope you guys don't think I'm being to picky about this stuff. I just want to make sure this circuit works the first time around and do it as inexpensively and in as small a space as possible.

 

[IRstuff]

A OTP bipolar fuse PLD should be inexpensive?

TTFN