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Small signal model of circuit with Darlington pair and source follower.

Small signal model of circuit with Darlington pair and source follower.

Small signal model of circuit with Darlington pair and source follower.

(OP)
I have some issues with drawing the small signal model of the circuit (picture 1.) I get confused when there are multiple transistors, especially when they are linked together like the Darlington pair.

This is the attempt I have made so far.

Could someone tell me if the redrawn circuit is correct?

RE: Small signal model of circuit with Darlington pair and source follower.

Doesn't look right to me.

-E is not the same as "-"

There are no capacitors?

RE: Small signal model of circuit with Darlington pair and source follower.

-E is a negative supply, which is what's needed for a circuit based on PNPs and a p=channel JFET. It should have been pretty obvious that something like R4/R5 is clearly a resistive divider, so paralleling them should have raised a red flag.

And, as itsmoked indicated, you seemingly removed all the capacitors, which would nullify your schematic for determining gross frequency response.

TTFN (ta ta for now)
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RE: Small signal model of circuit with Darlington pair and source follower.

(OP)
Hmm, now I am confused. I have followed my examiners' example when he did it for a circuit with one transistor. He says that one should do it as following: (1) ground the "-E" (2) capacitors short-circuited(3) Put in the small signal model for the respective transistor. That is what I have done here and is why for example R4 and R5 is parallell (both are connected to ground and to eachother). This is just a introduction course. But, if we dont look at the capacitors, is it still wrong?

RE: Small signal model of circuit with Darlington pair and source follower.

(OP)
Im sorry I did not explain it earlier, but it states in the assignment that C is large, and therefore not used.

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