The last book is targeted for MOSIS projects; is that what you're after? The layout is somewhat secondary, in my mind, to the ability to accurately model the layout for circuit performance. Presumably, MOSIS provides SPICE models that accurately reflect your selected processing node.

I've not been intimately involved in IC layout in over 25 years, but from a MOSIS perspective, each foundry and each processing node has a separate toolset: https://www.mosis.com/vendors/view/tsmc/design-kit...

Much depends on the depth of your pocketbook, and your desires on feature sizes: https://www.mosis.com/products/fab-processes

TTFN (ta ta for now)
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IR, I don't much care at this point if it's aimed at one specific foundry or another, I only care about general (individual) cell layout. Specific tools aren't my immediate need, either... if I can recognize a specific cell type by sight and I can talk somewhat intelligently about the process used to make it, that's perfect.

I had an opportunity 25 years ago to go down this path, but my career took me in a different direction. A recent opportunity would be significantly improved with more detailed knowledge, so I'm looking for something a bit more rigorous than random Google results. At the moment, I've started reading through Baker's book, but I'm interested in opinions on the other two and/or thoughts on books not on the list.

Dan - Owner
http://www.Hi-TecDesigns.com

For those looking at this thread some time down the road...

I'm about halfway through Baker's book (1200+ pages), and I have to say it's a really good read. Initial chapters lean towards MOSIS-related foundries and their specs, but honestly it makes sense to pick a set of specs to work with and show how it affects the basic design. Later chapters step away from foundry-specific rules and get into the design of specific modules (gates, charge pumps, PLLs, etc.). I will likely supplement this with some other books, but at the moment I think this will handle a good 75%+ of my knowledge seek.

Dan - Owner
http://www.Hi-TecDesigns.com

Would you consider writing a review of Baker's book, or a FAQ for this forum, when you're done?

STF

I can give it a shot, though I don't imagine it will be much longer than a few paragraphs. More than enough to make an informed decision, but as of this moment, I highly recommend it.

Dan - Owner
http://www.Hi-TecDesigns.com

Had some time today...



Title: CMOS Circuit Design, Layout, and Simulation, 3rd ed. (2010)
Author: R. Jacob Baker

Who is this book for:
VLSI engineers, digital/analog circuit designers, and any engineering professional/student who wishes to understand the underlying design and construction of CMOS circuits.

Assumed background:
Knowledge of linear circuits, microelectronics, and digital logic design.

Chapter breakdown:
Starting with an overall history of CMOS design, Baker quickly gets to the step-by-step process used in the creation of today's miniaturized CMOS elements. The book details the multiple chemical and physical processes through which a piece of ordinary sand is transformed into a silicon wafer capable of supporting millions of transistors per square inch. From the physics of a single diode, the book builds on this knowledge to show how these modern processes create the necessary elements of any design: resistors, capacitors, and finally MOSFETs.

As every design engineer knows, the road between theory and reality can be quite wide. With the basic element design now in your bag of tricks, Baker denotes those portions of the construction process under the designer's control (as well as those NOT under your control) and how those process choices affect the final element. Using the basic MOSIS foundry rules (MOSIS is a collection of foundries that make their services available to the general public), the book dives into the overall design of CMOS elements. This detail covers the range from proper spacing of individual elements on N-/P-doped layers to the connection of bonding pads on metallization layers. Throughout the process, the book provides example layouts, as well as potential shortcomings with each method.

Several chapters are dedicated to material a design engineer might deem "Datasheet Specs". No design is complete without a proper simulation of both internal an external effects, but such simulations require detailed information to be considered complete. The book lays out the various noise sources encountered, followed by developing models for both analog and digital simulation (SPICE) of MOSFETs. As with earlier chapters, care is given to point out what factors are under the designer's control, as well as how to mitigate those that aren't.

The remaining chapters (which account for nearly 70% of the book) tackle major design elements individually. Beginning with the simple inverter, the book builds on previous material to create larger blocks common in many designs: PLLs, Op-amps, data converters (ADCs and DACs), SRAM/Flash controllers, etc.

My take on it:
Despite the weighty topic, Baker does a surprisingly good job at balancing the theory & math with the reality & implementation of designs. For those deep-dive adverse (or those who simply wish more of an overview), the sections on noise and SPICE simulation can be skipped with no real consequence to the overall understanding; also, once the fundamentals have been secured in the earlier chapters, skipping around/between later sections would probably not cause too much difficulty. I found his comments on both the pros and cons of a specific design to be particularly useful from a designer's viewpoint.

Examples/problems (with solutions) are featured heavily throughout the text, and each chapter ends with a series of homework-style problems (no solution given) for teachers wishing to use the book as a classroom text. The book's material is supported via his website ( http://CMOSedu.com ), and a lot of simulation-based material that was originally in the 1st and 2nd edition of the book have been moved there. Book errata can also be found there, as well as reader emails and questions he has been asked over the years.

Overall, I found this book to be an excellent read. One nitpick I have is some grammatical issues (particularly missing/misplaced commas) can make the meaning of some sentences difficult to grok. Considering this is a 3rd edition, I would have expected issues like this to have been discovered and removed by now. Also, his foundry process discussion is (roughly) limited to the 50nm level; while quite good for most designs, I'd love to see the book updated for today's current process (sub-10nm) as there are significant new challenges involved in designing with elements at that size.


Dan - Owner
http://www.Hi-TecDesigns.com

Okay, so the review was a bit longer than I had imagined. When I'm done with this one, I'll likely take a look at his other book, CMOS Mixed-Signal Circuit Design.

Dan - Owner
http://www.Hi-TecDesigns.com

Thanks!
Star for the correct use of the word "grok".

STF