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Model of CPLD I/O

Model of CPLD I/O

Model of CPLD I/O

I am trying to look at the effects of filtering the outputs of a XILINX XC9500 family part in order to cut down on EM emissions and susceptability.  I am not interested in getting into the whole IBIS thing offered by XILINX.  I have a simple SPICE simulation set up, and would like to model the output characteristics of this part looking into various filter designs to see what effects these filters have on pulse delay and distortion.  If anyone here has an idea of the output impedance of this part family, please let me know.

RE: Model of CPLD I/O

When I want to model a digital source as an analog source this is what I do.  Below I'm referencing the DS064.pdf file for the XC9536 from the Xilinx web-site.  

p. 3  VOH (5V outputs) : (5V-2.4V) @ -4 mA = 650 ohms to 5V

p. 3  VOL (5V outputs) : (0.5V-0V) @ 24 mA = 20 ohms to GND

So on average (assuming a square wave output) you have an output impedance of 335 ohms.  That gives a first order estimate.  Note that if you are using 3.3V outputs you'll get different values from the tables!!!  

Note that for a capacitve load you'll have very different rise and fall times (RC time constants) off this output.  Thus for a second order evaluation you might need to model both sources independently.  You might also need a fancy termination (to GND and 5V).  

That will get you started.  Happy New Year!  

RE: Model of CPLD I/O

Oh, and the second thing i would do typically is to add a lot of series resistance on the output so that the output impedance variation is less.  Right now the output impedance on the XC9536 change by a factor of over 32:1 (650/20).  Putting a 2K resistor in series with the output drops is to 1.3:1 (2650/2020) and that is much easier to process with a filter.  

Of course, this assumes your application can handle the much slower timing of this new circuit.  

RE: Model of CPLD I/O

Thanks Zapped.  
I had come across an excellent TI document dealing with their '74 logic families, and came up with a similar answer.  The document number is SZZA008, FYI.  There you will find VI curves for all their 5V logic families for both input and output.  By doing an eyeball differentiation of these curves, I came up with an "average" of about 325 ohms, which was good enough to complete my model.  Unfortunately, my application is  pretty much intolerant of the delay I would incur by installing a series resistor in front of my filter, as this is a time-critical signal to a radar TR switch.  I also did the sanity check by looking at the single points given in the XILINX data sheet, and found that it fit my dV/dI estimate pretty well for the HC family curve I took my data from.

RE: Model of CPLD I/O

Good for you.  If you are getting into emissions issues with this part make sure you check your power traces.  They are a typical source of EM from digital parts.  Good luck.  

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