Simplest -- for TTL logic -- : ( 4 nodes ). Needs 2R-s and
1 C.
1.) input( from TTL) --- CAP.1
2.) CAP.2 --- R1.1 ---R2.1 --- output (to 1 TTL load)
3.) R1.2 --- gnd
4.) r2.2 ---Vcc
R1 = R2 = 1k
The output is normally vcc/2 (2.5 V). On the negative edge of the input the output drops below the "0" logic level (.8V) until the C discharges through the R-s bacl to original level.
The negative pulse is about R * C/4 long i.e. with 1Kohms and 1000pF in the range of 250nS.
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