HamiltonWoods
Electrical
- Mar 8, 2004
- 2
I am submitting a quote for an AD DL06-based system that the specification calls for "stage or state programming". I used to program using steps per the Whirlpool Standards for Industrial Equipment document of January 1993. Lately, I have converted over to state machines using integer addresses, one for the top-level state machine and one for each "subroutine" section, each of which is implemented as a state machine (I call those substates). Keep in mind that because I work with PLC's from an array of manufacturers, I implement "subroutine" sections in a way that does not use subroutine call statements (for instance the AD Click does not allow a subroutine to call a subroutine). Basically, a "subroutine" section is "called" by setting a "call subroutine" bit that is reset in the "subroutine" section at the end of its execution.
I was not aware of stage programming, so I have a few questions:
1) Is it likely that "stage or state programming" could be translated as "use stage programming or use state programming" or is it more likely that it should be translated as "use state programming implemented using stages"?
2) Are there any discussions regarding multistaging (top-level state calls lower level state machine)?
3) Is there a way to reuse a "subroutine" section in multiple stages, or does each stage need its own copy of the "subroutine" section.
4) I have always mapped inputs at the top of the scan and outputs (with interlocks) at the bottom of the scan. It appears to me that the last stage includes all the rungs after its definition until the END statement. Would the outputs therefore have to be placed before any stages?
Thanks for any help
Hamilton Woods
I was not aware of stage programming, so I have a few questions:
1) Is it likely that "stage or state programming" could be translated as "use stage programming or use state programming" or is it more likely that it should be translated as "use state programming implemented using stages"?
2) Are there any discussions regarding multistaging (top-level state calls lower level state machine)?
3) Is there a way to reuse a "subroutine" section in multiple stages, or does each stage need its own copy of the "subroutine" section.
4) I have always mapped inputs at the top of the scan and outputs (with interlocks) at the bottom of the scan. It appears to me that the last stage includes all the rungs after its definition until the END statement. Would the outputs therefore have to be placed before any stages?
Thanks for any help
Hamilton Woods