signal processing for medical application signals.....

[IC78]

hi... got a question guys... i am working on a 16-bit ADC IC to convert analog signals of low amplitude and frequency. I am goin to use the dual-slope architecture. After some calculations, i discovered that the frequency of the clock needed is too high (MHZ)...So the idea is working on 8 bits at a time using the same architecture to reduce the clock frequency. Is this possible and how do you combine the 2 8 -bit data to get the 16 bits again?

 

[nbucska]

You can't combine two 8 bit ADCs to make a 16 bit unless
both are 17 bit accurate -- and they are not.

What kind of sample rate do you need ? Any other limitation?
<nbucska@pcperipherals.com>

 

[Lewish]

Why is the clock frequency too high? Most ADCs will work just fine at lower than maximum specified clock rates.

 

[IC78]

Sampling rate is min 500Hz..... I was thinking that of the clock frequency is too high, signals may not be latched accurately. Do you guys have any circuit for overranged detection?

 

[melone]

Why not go to a higher sampling rate ADC?

 

[Lewish]

The sample and hold unit in the ADC will be accurate for the sampling range specified for the device. The output will be latched accordingly. You just need your external interface to keep up with it.

500 samples per second it not a very high acquition rate.

Over-range occurs when the input level exceeds the allowable input value of the ADC. Thus you get xFF as your output value.