I need to come up with a QPSK demodulator circuit for use in receiving the upstream traffic from a settop box. The QPSK signal will have a bandwidth of ~2 MHz and I can set the carrier frequency anywhere between 5 and 42 MHz. I have seen both analog and digital implementations. I was wondering if anyone had experience in this area and could make any recommendations. As always, recurring cost is important. However, I am willing to pay for an FPGA IP core if necessary. I have also seen people use DSP implementations. I have DSP experience and would entertain those implementations as well. Any thoughts?
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QPSK Demodulator
- Thread starter mbiegert
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As a generality, the industry seems to be heading the way of digital solutions. The bandwidth you are looking at may be within range of some late generation DSP but if not, processing in FPGA would certainly meet the bandwidth. Xilinx and others would have more connections to whatever IP you may want.
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