Power dissipation in open drain CMOS

[pleigh]

I was told that an open drain CMOS requires a passive pullup resistor at the output pin. But what happens when the ouput is active low? Isn't it sinking current from the pullup and inefficiently consumes power?

 

[melone]

It will only draw current when the output is active (pulling the output low), otherwise, it will draw 0 current (one side of the resistor is connected to power, while the other side is floating). That is the whole point of an open-collector/drain output. Therefore, many outputs can be connected to the same line, and any or all of them can assert the line (pull it low). The most simple example of this would be a common reset line.

 

[pleigh]

Thanks melone for your post.
I thought that open drain outputs formed an AND function, and the inactive state is low. May be at an internal transistor level, it is an AND but at the board level, it makes sense that it is an OR (only one reset line needs to be active for the system to reset).

 

[IRstuff]

It is an AND (for positive logic) and NOR for negative logic.

TTFN

 

[Comcokid]

Open drain output are also useful for logic level translation (3 V to 5 V logic, etc). Also useful for circuits where there is more than one voltage supply which may be off, and you want to avoid the logic output from trying to power the next unpower gate through it's protection diode.