As an example waste elimination, I cite what the Japanese were doing at their heyday. We got to second-source a Hitachi CRT controller chip, that Hitachi was second sourcing from Motorola. The mask set arrived with no test chips, which was completely counter to our internal products which had 5 test chips per wafer; that meant that 5 possible product sites were non-productive. We asked Hitachi about that and they said their process didn't require test chips!! The mask set came without a process flow and processing parameters like oxide thicknesses and ion implant densities/energies, so we asked for those, and they said, "don't worry about it, just run whatever your standard NMOS process is.
Disbelief... We ran the first lot; it yielded better than ANY chip of our own, and the second lot yielded even better. So, a couple of takeaways:
> lean manufacturing is about building robust product that survives the vicissitudes of a varying process, which means,
> designing a robust product that can tolerate process variations and provide product that fully meets its requirements without having to cherry-pick
> you must know and fully understand your production process, to the point where you can understand exactly every variability in the process and be able to design around them -- this means that you're looking beyond SPC and mean/tolerance range, because those alone don't tell the whole story. -- where humans are involved in machining, there's always been a lackadaisical attitude that trying to hit the center of the range was too much work, and that anything that came in under the limit was acceptable -- I think this was the root of many of the problems of US manufacturing in the 70s and 80s.
While there's some built-in cost to make Design for Manufacturing (DFM); the savings are tremendous:
> no test equipment and test chips dedicated to characterizing the process on EVERY wafer; that amounted to about $15 extra revenue per wafer and the elimination of about $500k of test equipment, AND elimination of test time
> there was always jokes in the manufacturing line about yield crashes every fall and summer, because the plant water supply changed because of snow/rain -- but this product was immune the those sorts of yield crashes
> even though the chip was larger than needed, it yielded better than chips that were tailor-designed for our own process, to the tune of about 30% higher yield. THAT translated into $150 extra revenue per wafer
TTFN (ta ta for now)
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