Improving Setup and Hold timing

[ibs81]

Hi I was wondering what is the best way one can improve setup and hold timing with the 90nm technology. As in what would be ones approach in trying to figure out what you needed to do in a circuit. Thanks for any help.

 

[itsmoked]

I, for one, do not understand your question.

 

[IRstuff]

Is this homework?

TTFN

 

[ibs81]

Nope its not for HW. I just started work at a DRAM company, and one of my tasks is to figure out how I can improve the Setup and Hold timing of a particualr circuit for the data path block.

At ceartin corners, the circuit is not functioning because of poor setup and hold timing, so I was wondering what is the process in how to improve that in general with any circuit.

 

[IRstuff]

Then, you need to start reading IEEE Journal of Solid State Circuits and the proceedings of the Internation Solid State Circuits Conference for the last 20 yrs.

Your question is specific to your company's presumably proprietary circuits, so you need to do measurements and simulations.

TTFN

 

[nbucska]

I think your boss knows the answer...

<nbucska@pcperipherals DOT com> subj: eng-tips
read FAQ240-1032

 

[designchain]

Uhhh, yeah - I agree with IRstuff and nbucska. Do a little (or more likely a lot of) simulation and you might figure it out...

Mike

--
Mike Kirschner
Design Chain Associates, LLC

http://www.designchainassociates.com