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Imbeded nails test system

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Kinsrow

Mechanical
Dec 5, 2005
94
Hi,

I'm doing PCb board test system which incorporate 200-300 test points using pogo pin to test it. I'm having problem with the hardware. In this case, the G-10 ( fiberglass)plate where we press in the pogo pins. I need the locational tolerance less than .002" in order to work properly. Is there anyone out there that can do hole positioning tolerencan +/- .002 or less on G-10 Plate with pin holes is .039". The test pad is .020" SQ.

Anyone out would like to share their experience on this?

Thanks
Kinsrow
 
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Even if the hole is right on, the tip of the PPin may be displaced with a few mils.

I think either the circuit or the PCB should be redesigned...


----------------------------
Please read FAQ240-1032
My WEB: <
 
No way can you press a pin into G-10 that thin and maintain position to .002, even at the plane of the G-10, much less at the tip of the pin. You'll also be able to displace the end of the pin with your finger.

You need a thicker, less anisotropic material.



Mike Halloran
Pembroke Pines, FL, USA
 
Is it 2 layer or more ?

Is it analog,digital or mixed? Are you so space limited,
that you can't add larger contact pads ( e.g. 1/2 mm square )?

I think you have an impossible job and a significant
redesign is indicated.







----------------------------
Please read FAQ240-1032
My WEB: <
 
The G-10 is .25 inch thick. We've been doing it by luck. Lately we're running out of luck.

What is anisotropic material?

Thanks
Kinsrow
 
Kinsrow:

Mike agrees that the job as you defined is impossible.
That is all. Now let's see if we can find any solution.
I am afraid it will not be painless or cheap but
-- if you are lucky -- possible.

Please answer:

Analog/digital? what is the size of the board, how many
layers?

Approx. how many percent of the surface is covered by parts ? Are parts on both sides ?

What is the maximal frequency?




----------------------------
Please read FAQ240-1032
My WEB: <
 
I'm not sure if this is digital/analog. I know that the test system is used for configging, programming, and testing of the PCB boards. I'm assuming it is digital. The board size is 8" x 8" and they are at least 2 layers. Components are both sides, but luckly the test points are on one side only. Roughly 20% of surface is covered by parts. I have fixed the issue by cutting a chunk of the G-10 that has bad holes with e a custom machined G-10 plate and re-drill the holes. It seems to work, but this is not a good fix for long term. The test pad is .020" sq (1/2mm sq) already.

How do you guys do it out there? There's got to be away to do this better. There are gizzilions electronic products out there?. They do boundary scan already, but I still got hundreds of test points to test.


Redesigning board is out of the questions, when they do they add more component and test points.


Thanks
Kinsrow
 
A test pad of 0.020 is totally inadequate. Just talk to the test pin manufacturers. Think about 0.050 for the next ones.

If you don't want the designers to change the boards perhaps you can work this out with the your PCB supplier. Ask them to enlarge the test pads up to 0.050. With their CAM tools this is an easy task and it will automatically flag any line spacing violation, which they can probably correct too.
 
It sounds like test pin diarrhea too. You start getting over 20 maybe 30 points you need to start asking why the designs are such cr@p that all this needs to be probed. That's the point of designing a product to be robust.

It sounds like the designers have no qualms about lobbing test points everywhere...

I'd suggest you start figuring out how much it actually costs per test point and start working on management to point out that these over generous test arrays are coming right out of the bottom line somewhere.

At some point, far below your point, it starts making sense to put testing into the board since that would be cheaper than probing 200 points on every board. That also allows the product to report problems in the field!

Keith Cress
Flamin Systems, Inc.-
 
I ask .035" SQ test pad and their respond is that it becomes a routing and signal integrate issue due to longer trace lengths and routing when we have several hundred test points, let alone .050" SQ test pad. How does HP and those other big boys do? They got PDA, cell phone that have small components. Don't they test the Main PCB at all. Maybe they don't. If it brokes just throw it away and get a new one, it's cheaper than having it fixed probably.

Thanks again,

Kinsrow.

 
I can't see any way to avoid redesign.
I think these are your choices:

1.) Reduce the TPs number by better selftest
2.) add more layers to create space for larger pads.



----------------------------
Please read FAQ240-1032
My WEB: <
 
Testing in a bed of nails is a matter of what equipment is available for test on the production floor. The bed of nails will more than often check for shorts/opens and be able to measure passives. Logic elements can also be tested functionally but the designers have to design for it for good test yields.

With the increased density of circuits, bed of nails tend to disappear (it just becomes not feasible to have so many pads for test) to be replaced with jtag and flying probes. Again the product has to be designed for it, and the complexity and cost of such test equipment and the development goes a step up.

Going with such techniques also involves large volumes, and a consequential increase in the yield of good products. Then like you say just the easy repairs are done and the rest is thrown away. Also many of the chips used in cell phones are custom made, with testability in them. Don't ask where do the defective units go when they're sent for repair.

Then you are stuck with designers that aren't interested in helping production to improve. It is your problem, right? You complainer! Welcome to the harsh world of low volume high-tech.
 
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