How to speed up Fmax

[swb1]

Hi,

I put a timing requirement on my clk signal and after I run through synthesis (VHDL code), I get a warning saying that Fmax could not be met. The part is pretty full (98%) and I can't change the part at this point in time. Any suggestions on how I can speed up Fmax??

Thanks,

swb1

 

[IRstuff]

Make your logic paths shorter.

TTFN

 

[swb1]

The pin fan out on the clk signal is 356. The part is pretty full. How can I shorten the logic paths??

Thanks,

swb1

 

[IRstuff]

But is that the problem? Is Fmax not being met because the clock can't run fast enough or because the logic delay through your logic is too slow?

These are not problems to ask random strangers, since they require detailed analysis of your design and application. You should be consulting the other engineers at your company.

TTFN

 

[sreid]

The program should tell you which path(s) have too much delay. You may be able shorten these by hand mimizing the logic.

 

[Noway2]

You also need to consider the architecture of the logic elements in your device. While your VHDL code will synthesize into something that works, often times different constructs and syntax statemetns will implement differently which can impact the performance. This is highly platform specific so I can't give you absolute details.

Look for statements that cause multiple loops through the same logic device as this can add a tremendous amount of delay to the processing. Use the reports from the synthesis tool for help in determining where to start.

Unless you can find a way to trim the amount of logic down, I think you really should look at a larger device. While it is a personal opinion, I think if you area already at 98% capacity and working on the new design that you are asking for trouble, at least in production if not in development.