Generating a "one-shot" pulse that truly occurs once

[oktane]

Hello,

This is probably a simple question for most of you, so hopefully I will get lots of replies.

I need to build a circuit that will go high for 0.5-3.0 seconds upon seeing a high input, and then go back low after that time REGARDLESS of the state of the input.

It must now virtually "ignore" the input and not respond until power is cycled to the chips.

I know about 555 timers in "one-shot" mode, but the problem is since the trigger input will not necessarily return to an inactive state, and repeat triggerings is unacceptable.

Any ideas?

Thanks!
-oktane
oktane@email.com

 

[MMAshwin]

Hi,

Do you have to build a circuit or can you just use a chip.

If its the latter then then look at the 74XX221 (where xx can be LS,HC,etc). Its a non retriggerable monostable whos output pulse width depends on an external Capaitor & resistor (you select them) and the width can vary from 30ns to 70Sec. What's more you get two of them on the one chip and you choose if you want it -ve or +ve triggered.

Check out the data sheet below:-

http://www.fairchildsemi.com/ds/74/74VHC221A.pdf

If you have to build it from scratch then any monostable circuit will do the trick, you just need an additional lockout circuit.
The input trigger is ANDed with the NOT Q of a RESET flip/flop (Q=0 & NOTQ=1). The filp/flop is SET by the output pulse from your monostable (this makes Q=1 & NOTQ=0). Any subsequent triggers are ignored until the flip/flop is reset.
For the flip/flop you could use a JK, D type or just a couple of cross coupled NANDs would do.

Check out the data sheet below for flip/flops:-

http://www.fairchildsemi.com/ds/74/74LVX112.pdf

JK Flipflop

http://www.fairchildsemi.com/ds/DM/DM74LS74A.pdf

D-type Flipflop

Any help ?, yes no let me know.

Regards

 

[oktane]

Laffalot,

Thanks, that helps a lot. I don't specifically need to build a circuit, so a single-chip solution would work fantastic. I like the 74xx221 chip you pointed out, however the datasheet seems to suggest that it will only be inhibitied if I keep the NOTA pin high.

The datasheet says "the VHC221A is not retriggerable until the output pulse times out."

In my case if I have the output set to 1 sec, does that mean it will again be succeptibe to triggering? In order to inhibit triggering it says to make the NOTA pin HIGH, which would require using a latch as you mention in your flip-flop example, right?

Space is somewhat of a concern, and so I have to maximize the existing logic on the board. I have access to another D-flip-flop with PRESET and SET, and will be adding the 74xx221 hopefully.

So theoretically I could use the 74xx221 to trigger the D and make it change state via a PRESET/SET command. This would feed back to the 74xx221 and inhibit it, correct?

My one question is in what state does a flip-flop start off if it's not "initialized"? Is it a random 0, 1, or a float?

Hope this message made sense, it's hard to follow even for me!

 

[MMAshwin]

Hi again,

Is your trigger rising or falling ?.

Lets say its rising.

On the 221 IC pull pin 1 (not A) to 0v through a 4k7 resistor and apply the trigger input to pin 2 (B.

As the trigger goes from low to high the monostable is triggered.

Apply the output of the monostable to the CLK of your D-type with the D input held high (make sure its cleared first more on that later). Q will go from 0 to 1 and apply this to pin 1 (not A) of the 221 IC. This will inhibit any further triggering.(See page 2 of the data sheet)

Now as for the D-type. I remember long ago when we used to design these things in transistors !, you could not anticipate the start up condition because it depended on the speed of the gates/internal capacitance etc.
So the best thing to make sure it starts in a reset state (i.e. Q=0) is to hold the Preset High through a pull up resistor and the Clear is attached to the middle of a RC network where the R is connected to Vcc and the -ve of the cap connected to 0v. On power up the capacitor is originally at 0v and takes time to charge up through the resistor R. The bigger the values the longer the time (I use 1Meg & 1uf to be sure). This holds the b]C[/b]lear low for a short time after Vcc has been applied.

+5v ----/\/\/\/\---o-----||---- 0v
|
|
To Clear

Make any sense ? If not let me know & I'll draw a schematic.
Any help ?, yes no let me know.

Regards

 

[MMAshwin]

Hi,

Oops after submitting the post the graphics went wonky. The line to the Clear of your D-type should be connected to the junction of the resistor & capacitor.

Also I forgot to mention if your trigger is falling then you just have to reverse the pin connections and apply the not Q to the B pin which is pulled up.
Any help ?, yes no let me know.

Regards

 

[oktane]

Excellent! Your information was very helpful, as this seems to be exactly what I need. Thanks for taking the time to think through these details for me!

I especially like your idea about using an RC circuit for ensuring a "0" startup state. Ingenius!

My one question is what will happen once power is removed from the circuit. Will the capacitor discharge sufficiently to allow for the "0" state to be initialized the next time the circuit is started up? I think it will, but my physics is rather rusty.

So after power is removed the circuit looks like:

0V--/\/\/\---||---0V
|
|
D-flip CLR

This would equalize the charge on the capacitor, effectively shorting it out, right?

 

[MMAshwin]

Hi again,

Yes your right. Of course the length of time for discharge will depend upon the capcitance of the capacitor and the resistance of the resistor.

It maybe that the power is not of long enough to discharge the capacitor fully (unlikely though).

If you think that this would be a problem then put a reversed biased diode in parrallel with the resistor.

When power is applied the diode will be reverse biased and the capacitor charges though the resistor. When power is removed the capacitor will discharge through the diode as the +ve rail has dropped to 0v and the diode is now forward bias.


|---|<|----|
| |
0V-o--/\/\/\/\-o-||---0V
|
|
D-flip CLR




However in practice the length of time the power is off is significantly longer than the CR discharge time. Any help ?, yes no let me know.

Regards

 

[oktane]

Yes, that seems great.

You sure know a lot about electronics!

-oktane

 

[MMAshwin]

Hi,

Thank you.

I see you joined the community (no longer a visitor). Welcome ). Any help ?, yes no let me know.

Regards

 

[jbartos]

It appears that a little clarification in the original posting is needed, namely, do you mean the high input positive only or &quot;positive or negative&quot; in &quot;I need to build a circuit that will go high for 0.5-3.0 seconds upon seeing a high input, and then go back low after that time REGARDLESS of the state of the input.&quot;?

 

[scoty]

I have did this before by using a 555 timer (use pullup resistor if trigger is rising edge) and capacitor for the trigger network. This will work to &quot;filter&quot; the trigger signal and will turn it off even if trigger is still activate. Good luck