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FPGA Thermal Conductivity
- Thread starter rodneyb
- Start date
MikeHalloran
Mechanical
I don't know how you're expected to model FPGAs; it's been a long time since I did any packaging.
If you were trying to cool transistors, I'd have to ask how you could possibly infer the junction temperature, which is what you would be trying to control with the cooling, if you didn't know the thermal resistance from junction to case. And I'd have to suggest that you have to know the thermal resistance, and the dissipation, of each transistor, so that you could figure out which one was going to be the worst case.
Mike Halloran
Pembroke Pines, FL, USA
If you were trying to cool transistors, I'd have to ask how you could possibly infer the junction temperature, which is what you would be trying to control with the cooling, if you didn't know the thermal resistance from junction to case. And I'd have to suggest that you have to know the thermal resistance, and the dissipation, of each transistor, so that you could figure out which one was going to be the worst case.
Mike Halloran
Pembroke Pines, FL, USA
Rodney,
If you model a chip package as a homogeneous block you won't be able to correctly determine it's junction or case temperature. This type of model is only recommended if you:
1) don't have better data and
2) expect it to have ample margin and
3) are only modeling it to estimate it's effect on other devices that may be marginal
#1 is actually a poor excuse since you can usually get enough data to do better than a simple block.
Or, perhaps the enclosure model is too large to include chip package details? If so, create a detailed model of the chip package and use the local results of the enclosure model as the boundary conditions.
ko (
If you model a chip package as a homogeneous block you won't be able to correctly determine it's junction or case temperature. This type of model is only recommended if you:
1) don't have better data and
2) expect it to have ample margin and
3) are only modeling it to estimate it's effect on other devices that may be marginal
#1 is actually a poor excuse since you can usually get enough data to do better than a simple block.
Or, perhaps the enclosure model is too large to include chip package details? If so, create a detailed model of the chip package and use the local results of the enclosure model as the boundary conditions.
ko (
I forgot to mention that even the simple block model should include the component power.
ko (
ko (
- Thread starter
- #5
I have added the power and separated the die (heat source) and chip package, but I would still like to simplify the component as much as possible.
Do you have any suggestions? This is a system level analysis and most details will have to be ommited.
Thanks,
R
Do you have any suggestions? This is a system level analysis and most details will have to be ommited.
Thanks,
R
Rodney,
If the system model really can't handle any chip detail, you have to create a 2nd model (either chip-level or board-level) and do the following:
1. Solve the system model and note the local results near the area of interest (that is, the local air temperatures and velocities near the chip or board).
2. Create a detailed model of the chip or board and use the local results from your system model as the boundary conditions.
3. Sometimes the heat and air paths are significantly different in the detailed model, which in turn may effect the local boundaries. If so, you'll need to iterate: tweak the blocks in the system model to behave more like the detailed model, re-solve and use the new boundary conditions in the detailed model.
In my experience this technique is rarely necessary anymore thanks to compact chip models, improved grid/mesh control, and more powerful computers. If you're not already taking advantage of these, you may be able to avoid a tedious analysis.
ko (
If the system model really can't handle any chip detail, you have to create a 2nd model (either chip-level or board-level) and do the following:
1. Solve the system model and note the local results near the area of interest (that is, the local air temperatures and velocities near the chip or board).
2. Create a detailed model of the chip or board and use the local results from your system model as the boundary conditions.
3. Sometimes the heat and air paths are significantly different in the detailed model, which in turn may effect the local boundaries. If so, you'll need to iterate: tweak the blocks in the system model to behave more like the detailed model, re-solve and use the new boundary conditions in the detailed model.
In my experience this technique is rarely necessary anymore thanks to compact chip models, improved grid/mesh control, and more powerful computers. If you're not already taking advantage of these, you may be able to avoid a tedious analysis.
ko (
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