CarbonWerkes
New member
- Mar 15, 2006
- 62
Hello
I have an application which will involve 2 microcontrollers and an SPI-based accelerometer. The Primary controller is heavily tasked, and therefore requires the support of a Secondary controller to handle integrations from the accelerometer data.
All devices have a single SPI module.
Im concerned about a daisy-chain connection bus with this setup. Im not sure that the accelerometer(s) have an SDO port (or support daisychaining), and there may be some clock limitations (least common denominator).
What I wonder is- can I use a dual master config, where the Primary connects to the Secondary, and where the Secondary connects to the accelerometer. The implication here is that the bus will be cross-wired between the Primary and the accelerometer (i.e. SDO<->SDO, SDI<->SDI). Yes, there will also need to be some additional inhibit signal between the Secondary and the Primary, so that if the Secondary were communicating with the accelerometer, the Primary would not attempt to initiate a connection with the Secondary.
My understanding is that, unless the CS pin is held low, the SDI/SDO pins on a device should remain in high impedance mode, and as such should not affect signaling on the bus. That is, unless the accelerometer's CS is held low by the Secondary uC, it would ignore any bus signaling from the Primary uC, and since it would be in high-impedance mode, it would not affect the signals, nor be affected by them.
Apparently this is not a common topology, but Microchip thinks it would work (but is untried there). Does anyone have any insight on this?
Best,
Rob
I have an application which will involve 2 microcontrollers and an SPI-based accelerometer. The Primary controller is heavily tasked, and therefore requires the support of a Secondary controller to handle integrations from the accelerometer data.
All devices have a single SPI module.
Im concerned about a daisy-chain connection bus with this setup. Im not sure that the accelerometer(s) have an SDO port (or support daisychaining), and there may be some clock limitations (least common denominator).
What I wonder is- can I use a dual master config, where the Primary connects to the Secondary, and where the Secondary connects to the accelerometer. The implication here is that the bus will be cross-wired between the Primary and the accelerometer (i.e. SDO<->SDO, SDI<->SDI). Yes, there will also need to be some additional inhibit signal between the Secondary and the Primary, so that if the Secondary were communicating with the accelerometer, the Primary would not attempt to initiate a connection with the Secondary.
My understanding is that, unless the CS pin is held low, the SDI/SDO pins on a device should remain in high impedance mode, and as such should not affect signaling on the bus. That is, unless the accelerometer's CS is held low by the Secondary uC, it would ignore any bus signaling from the Primary uC, and since it would be in high-impedance mode, it would not affect the signals, nor be affected by them.
Apparently this is not a common topology, but Microchip thinks it would work (but is untried there). Does anyone have any insight on this?
Best,
Rob