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A/d converter design concepts 1
- Thread starter mukund
- Start date
Hi Mukund,
I became a member of this group after a long long time since u have posted your comments on A/D converter. I would like to know which method is more applicable to design an A/D converter upto a speed of 100MEG and what are the problems that can be faced while doing it in sigma-delta conversion.
Waiting for your reply.
Nasir
I became a member of this group after a long long time since u have posted your comments on A/D converter. I would like to know which method is more applicable to design an A/D converter upto a speed of 100MEG and what are the problems that can be faced while doing it in sigma-delta conversion.
Waiting for your reply.
Nasir
Hello mukund,I have been using high speed ADCs for the past 2 years now (~100MSPS) and would be glad to discuss any issues. I am also somewhat curious about attempting to design the 100MEG sigma-delta converter that Nasir mentioned. I haven't seen any sigma-delta type product ever go faster than ~200ksps at best. I didn't think the track and hold amplifiers were able to move fast enough to produce an end sample rate of anywhere near 100MEG using sigma-delta type conversion. I am curious to here more about this.
stelleb
stelleb
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1
- Thread starter
- #4
Hello Nasirq and stelleb,
I am working on pipelined structure of A/D converter design.I have not worked yet on sigma Delta structure.Pipelined structure is suitable for high speed like 100meg hz.I am not sure but I have heared that sigma delta is more precise but can not go at higher speed. Pipelined structure with error correction techniques gives the best results, both high speed and accuracy.Please let me know your views.
I want to know something about testing of ADC.What methods you apply?
waiting for your reply.
I am working on pipelined structure of A/D converter design.I have not worked yet on sigma Delta structure.Pipelined structure is suitable for high speed like 100meg hz.I am not sure but I have heared that sigma delta is more precise but can not go at higher speed. Pipelined structure with error correction techniques gives the best results, both high speed and accuracy.Please let me know your views.
I want to know something about testing of ADC.What methods you apply?
waiting for your reply.
mukund,
I am quite certain that given a choice most folks would choose to obtain a sigma-delta type converter if it could match the sample rates of the pipelined types. However, I don't believe that this will happen any time soon. The reason that I don't think this will happen is that the effective number of bits as well as the speed of any ADC is determined by the speed and settling time of the ADCs track and hold amplifier in the front end. Sigma-delta type converters usually take several hundred times faster sampling clock sources so that the 1-bit ADC which is actually internal to the parts can effectively build the code inside the part to be dispensed at an effective sample rate several hundred time slower. Anyway, parallel type pipelined converters can achieve very fast output sample rates usually limited at this point by the type of digital outputs, unless you go with ECL or PECL types and then you become more limited by the front end settling time of the T/H amp again. As for testing of an ADC, I usually test for LSB jitter with the analog input/s held to both rails. In these high speed type converters, the sampling clock purity is the gold standard to achieve. I am currently reworking a PCB whose transmission line effects have managed to couple Fsck/2 into my Fsck signal to the ADC which has the expected effect of mixing the signal not only around every Fsck, but a nice little spur around Fsck/2. I know that I have gained more information from frequency spectrum examination both of the fundamental and first alias than I ever would have from time domain data from the ADC. Are you designing a circuit that uses an ADC or the ADC itself mukund?
stelleb
I am quite certain that given a choice most folks would choose to obtain a sigma-delta type converter if it could match the sample rates of the pipelined types. However, I don't believe that this will happen any time soon. The reason that I don't think this will happen is that the effective number of bits as well as the speed of any ADC is determined by the speed and settling time of the ADCs track and hold amplifier in the front end. Sigma-delta type converters usually take several hundred times faster sampling clock sources so that the 1-bit ADC which is actually internal to the parts can effectively build the code inside the part to be dispensed at an effective sample rate several hundred time slower. Anyway, parallel type pipelined converters can achieve very fast output sample rates usually limited at this point by the type of digital outputs, unless you go with ECL or PECL types and then you become more limited by the front end settling time of the T/H amp again. As for testing of an ADC, I usually test for LSB jitter with the analog input/s held to both rails. In these high speed type converters, the sampling clock purity is the gold standard to achieve. I am currently reworking a PCB whose transmission line effects have managed to couple Fsck/2 into my Fsck signal to the ADC which has the expected effect of mixing the signal not only around every Fsck, but a nice little spur around Fsck/2. I know that I have gained more information from frequency spectrum examination both of the fundamental and first alias than I ever would have from time domain data from the ADC. Are you designing a circuit that uses an ADC or the ADC itself mukund?
stelleb
hello to both of you.
Actually such a high-speed can be reached even by using oversampling converters, the only concept or the catch here is that the oversampling should be reduced. But there are definitely a lot of problems I have encountered in this design like a very high end digital filter, for simulation had to tamper the spice parameters etc.etc. but still it can be reached with a very very accurate design.
Nasir
Actually such a high-speed can be reached even by using oversampling converters, the only concept or the catch here is that the oversampling should be reduced. But there are definitely a lot of problems I have encountered in this design like a very high end digital filter, for simulation had to tamper the spice parameters etc.etc. but still it can be reached with a very very accurate design.
Nasir
Hello everyone,
I am new to this website and forum. I found this thread through a search for "ADC design concepts". I have no prior practical experience in designing pipe-line ADC but I will be starting to work on one soon. I would like to know whether is there a certain ic design methodology for pipeline adc from modeling, design, simulation to analysis. I have not been able to find anything comprehensive on the method for designing pipeline adc from scratch. What I found are literature that either just introducing basic adc concepts or the other extreme: interpreting test results.
Any comments or guidance will be deeply appreciated and please excuse me if I have violate any forum etiquette here.
thanks,
simon
I am new to this website and forum. I found this thread through a search for "ADC design concepts". I have no prior practical experience in designing pipe-line ADC but I will be starting to work on one soon. I would like to know whether is there a certain ic design methodology for pipeline adc from modeling, design, simulation to analysis. I have not been able to find anything comprehensive on the method for designing pipeline adc from scratch. What I found are literature that either just introducing basic adc concepts or the other extreme: interpreting test results.
Any comments or guidance will be deeply appreciated and please excuse me if I have violate any forum etiquette here.
thanks,
simon
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