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Silicon Chip structural failure problem

Silicon Chip structural failure problem

Silicon Chip structural failure problem

(OP)
We have an unusual Materials/structure problem involving a silicon wafer (P-type), cut in the form of a rectangular structure .77in x 1.25lg x .0285 Thick.  Support is along the long edges in four spots, .12" in from the short sides, reaching in .03"x.08"in.  We are applying 64 lbf distributed over the entire surface uniformly with an elastomer. The wafer is confined on it's sides by a .005" slip fit.  The wafer is heated very quickly to 95 degrees C.

The wafer breaks down the middle, from short side to short side. This failure is 40% of the time, after the load is applied, and after the heat is applied.  We reduced the applied force by half (34 lbs force) and the same amount of failure is occuring.  The problem appears to be uneven stresses, but I am not certain yet.   

I was hoping someone could tell me where to get some good mechanical properties for the material.  I have physically measured the thermal expansion of the materials involved and can not believe they are a factor.  If anyone has knowledge of a failure mode to look out for (shear, bending, impulse?) Please let me know.  Charlie2go@aol.com  

RE: Silicon Chip structural failure problem

First of all, you'll probably want to post this in a few other areas (I would recommend both finite element analysis and possibly one of the materials engineering groups). This area is more structural engineering--bridges, etc. (Don't feel dumb--I made the same mistake... )

I'll take a stab at it:

It appears that one could idealize your described structure by looking down the length of the chip such that one sees one short edge only.  This then devolves into (approximately) a plane strain problem of a cantilever beam. The beam is then .77" long, and is supported at .12" from each end.  

The applied pre-load then plays itself out as some kind of distributed load.  If one were to idealize this distributed load as uniformly distributed (large leap I admit), this would then result in a curvature of the "beam" structure with zero slopes at the support points and also at the mid-section of the beam.

So, what happens when the heat up occurs? Some ideas:
1a) I did some back-of-the-envelope calculations, and for my best recollection of thermal expansion coefficient of silicon, you may in fact be heating it significantly enough that the .005" gap gets taken up.  Any further expansion would play itself out as axial compressive stresses, which for the deformed configuration of the chip could result in high stresses at the centerpoint.

1b) You don't specify how strong the supports are relative to the chip itself.  If they are significantly stiff (thereby limiting in-plane motion of the chip), they could in fact induce significant thermal stresses between them (due to the thermal strains between them being "held"). This would also lead to high stresses at the centerpoint of the chip.

2) One additional thought: it is my recollection that silicon has a pretty low thermal conductivity. You haven't described the process by which you are heating the chip.  If it is being heated in the middle, there could be a significant thermal gradient, which could also increase these stresses.

3) Finally--you have already stated that there is an elastomer holding the chip in place. From this I am presuming that the chip (by whatever means you are heating it) is only being heated on one face.  Again, if my memory about silicon's low conductivity is correct, then this could result in a significant thermal gradient through the thickness of the chip.  Again, with the preloading the way it is, this would likely be most damaging to the mid-section of the chip.

In fact as I rethink my last point, I feel that this makes even more sense. The pre-load would cause center-line curvature which is convex from the heat source. The heat source would then result in further increasing the tensile stresses in the fiber nearest the heat source.  

I hope I've understood your problem as posed correctly. I apologize I can't be more thorough--all of my useful books are at work.  If I've committed a big gaffe on assumptions, correct me and I can think through this some more.

This was an interesting problem to work the noodle on.
Brad

RE: Silicon Chip structural failure problem

I think Bradh is on the right track...combined stresses.

You have a force normal to the flat surface of the chip, you have the thermal gradient causing curl of the surface, and you have thermal expansion causing a planar (axial) force along the axis of failure.

Essentially you have compressive stress and bending occurring at the same time.  For combined stresses such as these, a generalized check would be:

fa/Fa + fb/Fb < 1, where fa= axial compressive stress, Fa=allowable axial stress, fb=bending stress, Fb=allowable bending stress.

Realizing that your issue is planar and not uniaxial doesn't really change anything, other than the analysis is a bit more difficult.  FEA would be an appropriate approach to this and would give an accurate assessment of the stress distribution.  Even if you can find enough mechanical properties of your material, do the analysis with a known material as a surrogate.  In general, the stress distribution will be similar, though the magnitudes will differ.

RE: Silicon Chip structural failure problem

Raised a bunch of questions...

I assume the chip is connected or installed in some type of printed circuit board,  Is it by contact only, with the preload providing continuity?  Are the 4 supports actually pins and if so what type of tolerance occurs at the pins?  Do the supports restrain movement in any fashion?  Does the elastomer offer any tensile/compressive resistance?  Does the failure occur with only a single application of current or does it occur after several on-off cycles?  I assume that your artwork is located at the top of the wafer; is it well distributed over the surface of the wafer or is it local? centered?

I'm not sure about the failure location.  Is it parallel to the long face (short side to short side?) or is parallel to the short face?  Does it appear to initiate at the top or the bottom of the wafer?  Have you looked at the failure surface under magnification?  Can you describe the surface?  any sharp edges top or bottom? any conchoidal fractures at the side corner of the chip?

Does the applied force remain?  Something like a curved spring used to hold some processors in contact with heatsinks?  How is this uniformly applied? (By reducing this force by half and still having the same percentage of faillures, I wouldn't think it would be part of the problem).  How is the force determined?

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