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TSMC 65nm sealring LVS error

TSMC 65nm sealring LVS error

TSMC 65nm sealring LVS error

I am using TSMC 65nm PDK for tape out. The LVS was clean before I add the sealring. However, when I added the sealring, the LVS complaint about 2 things:

(A) Stamping conflict. Net VSS is selected for stamping.
(B) the additional nets and instance. The additional device from the sealring is a lot of parallel conected caps, called C(CM).

For (A), stamping conflict, I confirmed that it is due to the sealring has OD-CO combination and LVS consider it as a substrate pin. But the sealring is not connected to the core substrate VSS pin. The way I solved it was enclosing the sealring by pusb2 layer. Do you think this is the right way to do so? Or should I connect the seal ring to the core VSS?

For (B), I checked the LVS rule file and isolated the device and discovered that a subcell in sealring lib is the reason of this C(CM) device. The LVS rule considers the combined layers in the subcell as CM caps. By checking the LVS rule file I have, I can think of 2 ways to solve this LVS error. The first way is: I commented the line in LVS rule file that defines the C(CM). Then The LVS could not recognize the C(CM) hence it is clean again. The second way I can think of is that can I ask if there is a schematic or spice/LVS netlist file associate with the sealring layout? (for example, the ESD devices has no schematic but a spice model for LVS)

Thank you very much

RE: TSMC 65nm sealring LVS error

I suppose if you thought for some crazy reason that you were talking to someone intimately familiar with the TSMC PDK (whatever that is) and your design, your posting might make some marginal sense. This sounds like something you should ask your TAs, or professor, or even your TSMC rep.

TTFN (ta ta for now)
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