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# Implementing a phase accumulator using a Virtex FPGA

## Implementing a phase accumulator using a Virtex FPGA

(OP)
Hello everyone,

I am trying to implement a system which purpose is to generate a sin wave with a frequency specified by the user. I am thus designing a phase accumulator. below are my steps :

- As I have a 1-Gsps DAC, first I store 2^17 samples of one cycle of a 1-Ghz sin wave on a RAM.
- Then I calculate the phase offset : requestedFrequency(khz) * 2^32 / 1000000
- Finally, at each 1-Ghz clock ticks, I increment the value of my accumulator register (initialize with 0) with the phase offet. And I retrieves the 17-MSBs bits of the accumulator register output and I use this BUS to address my RAM and send the correct sample to my DAC.

I am going to be more precise concerning my real problem :

(sorry I am bad in drawing)

The brown signal above is a 1-Ghz signal. I consider I have stored 2^17 samples of one cycle of a 1-Ghz signal in a RAM.
Because the accumulator register wraps, we can imagine a serie of one cycle of a 1-Ghz signal as represented above by the brown signal.
If I want to generate a 250-Mhz signal, the accumulator register will increment by the phase step at each clock ticks to pointed to the crossing between the red vertical lines and the 1-Ghz signal. I will thus generate a 250-Mhz signal wich spectrum contains several additional frequencies (as shawn the purple signal above).

I hope being more clear. Have someone an idea ?

Thanks to pay attention to my problem
Replies continue below

### RE: Implementing a phase accumulator using a Virtex FPGA

The brown signal is not a 1 GHz signal, it is a 7.629 KHz signal generated with a 1 GHz clock:

1 GHz / 2^17 = 7.629 KHz -> 1 GHz / 7.629 KHz = 131072 samples per cycle; 1 count (each sample) equals 0.0000479369 radians.

So when you increment your 'phase' counter by one at every clock tick, you will get a 7.629 KHz sine wave with very nice fidelity.

1 GHz / 250 MHz = 4 samples per cycle -> 1 GHz / 4 = 0.250 GHz; 2^17 / 4 = 32768 counts per sample, so depending upon your phase delay, you'll get something like your figure shows. Your index through your look up table is 0, 32767, 65535, 98303, 0... so that is pretty coarse. Each step is 1.57 radians.

You've got the wrong architecture. If you can sample with a 2.5 GHz clock (10 samples/cycle) you might have something reasonable.

What frequency range do you need? If you passed this through a bandpass filter at 250 MHz it would look okay.

Z

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