SPI bus

[perts]

i have spi bus and i need to put caps on that clock line, for esd reasons. what value cap size can i put on that line before i start affecting the clock signal. I want to run the spi bus atleast 1 MHZ.

 

[cbarn24050]

Hi, the whole idea of installing the caps is to affect the signal otherwise there would be no point, mind you i'm not sure there is much point in doing that anyway. How much it degrades the clock edges depends on the clock source impedance. You also need to consider how much degradation the reciever will tolerate.

 

[felixc]

So you're on a new design? how about embedding the lines or "microstripping" them? About using ferrites in series? The layout itself may have a larger impact on EMI than its basic clock frequency, because of ringing and impedance mismatches.
Place the series and parallel termination parts, then use an scope to determine how nice the signal is at both ends.