Fluorescence
Electrical
- Oct 19, 2008
- 42
Hello,
I am writing with regard to the RMS capacitor current in the “valley filler” capacitors in an 8W off-line 1 transistor forward converter SMPS.
I cannot understand why the LT Spice simulator has calculated this charging current so low.
Here is the circuit……
*** FIGURE 1
The “valley filler” capacitors are C1 and C5 (each 4.7Uf, ESR = 56R) .
The LT Spice “SwitcherCAD” simulator calculates the RMS current in the top valley filler capacitor (C1) as 58mA .
***FIGURE 2
-(Here is the LT Spice simulation)
(Bus voltage in green, Capacitor current (C1) in blue)
(- Capacitor ESR = 56R for each valley filler capacitor)
-However 58mA is far too low, it could not possibly be correct.
If one were to consider the RMS charging current alone into the valley filler capacitors, then this comes out as 315mA RMS….
***FIGURE 3 ***
Here is a representation of the DC bus voltage (the voltage on the valley filler ).
The calculation of the RMS capacitor charging current for the valley filler caps is as follows………
-----------------------------------------
Bus Voltage = A sin wt
Cap charging current = C * d/dt (A sin wt ) [during interval X]
Considering the capacitor charging current alone (interval X), and calculating the RMS value of this charging current…….
……This comes out to 315mA for the capacitor charging current.
If one does not want to do an integration, then the capacitor charging current (which occurs during interval X on FIGURE 3 ) can (for this interval) be approximated as a triangle with peak value given by i(t) = C dv/dt = 870mA….
…then just use the equation in Linear Technology Application Note 46 (page 24, bottom of page).
Does any reader know why the LT Spice simulator has calculated the capacitor charging current so low ?
Also, if one regards the LT Spice waveforms in FIGURE 2 above, one can see that the waveforms are clearly erroneous…
The Simulation shows the C1 capacitor current discharging just after the peak of the bus voltage (interval Y in FIGURE 3)
-There is no way that C1 (or C5) can discharge in the interval (Y). –All of the valley filler diodes are reverse biased during interval Y and there can be no capacitor current. –though the simulator clearly shows capacitor current during interval Y.
Apologies for length of post, -would be most grateful for any thoughts on this
I am writing with regard to the RMS capacitor current in the “valley filler” capacitors in an 8W off-line 1 transistor forward converter SMPS.
I cannot understand why the LT Spice simulator has calculated this charging current so low.
Here is the circuit……
*** FIGURE 1
The “valley filler” capacitors are C1 and C5 (each 4.7Uf, ESR = 56R) .
The LT Spice “SwitcherCAD” simulator calculates the RMS current in the top valley filler capacitor (C1) as 58mA .
***FIGURE 2
-(Here is the LT Spice simulation)
(Bus voltage in green, Capacitor current (C1) in blue)
(- Capacitor ESR = 56R for each valley filler capacitor)
-However 58mA is far too low, it could not possibly be correct.
If one were to consider the RMS charging current alone into the valley filler capacitors, then this comes out as 315mA RMS….
***FIGURE 3 ***
Here is a representation of the DC bus voltage (the voltage on the valley filler ).
The calculation of the RMS capacitor charging current for the valley filler caps is as follows………
-----------------------------------------
Bus Voltage = A sin wt
Cap charging current = C * d/dt (A sin wt ) [during interval X]
Considering the capacitor charging current alone (interval X), and calculating the RMS value of this charging current…….
……This comes out to 315mA for the capacitor charging current.
If one does not want to do an integration, then the capacitor charging current (which occurs during interval X on FIGURE 3 ) can (for this interval) be approximated as a triangle with peak value given by i(t) = C dv/dt = 870mA….
…then just use the equation in Linear Technology Application Note 46 (page 24, bottom of page).
Does any reader know why the LT Spice simulator has calculated the capacitor charging current so low ?
Also, if one regards the LT Spice waveforms in FIGURE 2 above, one can see that the waveforms are clearly erroneous…
The Simulation shows the C1 capacitor current discharging just after the peak of the bus voltage (interval Y in FIGURE 3)
-There is no way that C1 (or C5) can discharge in the interval (Y). –All of the valley filler diodes are reverse biased during interval Y and there can be no capacitor current. –though the simulator clearly shows capacitor current during interval Y.
Apologies for length of post, -would be most grateful for any thoughts on this
