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Effects of transformers in parallel 2

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dgn07

Electrical
Feb 9, 2007
2
Hello all,

I am having a problem with dc offset on my signal when I try to drive a large number of 1:1 signal transformers
in parallel.

The input to the primary side of the transformer is a 64KHz DS0 composite clock pulse (i.e. alternating bipolar
pulses with 2 pulses in the same direction every 8th pulse). The driver is a Maxim 4180 current-feedback op-amp, and
there is a 10uf dc blocking cap in series on the primary side.

The dc offset is not apparent when up to 4 transformers are connected in parallel (secondary side outputs are
not connected to each other, and there is a 130 ohm termination on the secondary side on 1 of the transformers)
Cat5 cables with RJ45 connectors are used as the method to daisy chain and connect the inputs to the primary side
of all the transformers.

When a greater number of transformers are attached, I see a dc level shift during the time when the double pulse is
present. During this time, the dc offset would increase in steps and the 0V reference of the pulse when returning to
zero whould be shifted. Also the amplitude of the second pulse is attenuated by approximately 40%.

It seems like I have passed the threshold (of putting too many transformers in parallel), and this has resulted in
a decrease of inductance and thus saturating the transformers. Is this an accurate read?

Also, could the cabling and connectors add enough capacitance and contribute to the dc imbalance?

What can I can do on the driver side to rectify this problem?

Thanks for the help.
 
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Have you tried incresing the value of the capacitor? Intuitively that's the first thing I'd do.
 
Thanks for the feedback.

GS3, yes I've tried that. Doubled the series cap to 20uf, but did not see any appreciable difference.

nbucska, only 1 secondary (farthest from driver)had a 130 ohm termination load, while the rest had none.
 
Welcome to transmission lines!

"Cat5 cables with RJ45 connectors are used as the method to daisy chain and connect the inputs to the primary side
of all the transformers...

I see a dc level shift during the time when the double pulse is present. During this time, the dc offset would increase in steps and the 0V reference of the pulse when returning to
zero whould be shifted. Also the amplitude of the second pulse is attenuated by approximately 40%."

That sounds like you are getting reflections off each of the 'stubs' at each transformer. The farthest 'stub' is terminated in 130 ohms; what are the loads on the other stubs? Maybe you can try a series resistance at each of the transformers along the way to stop the reflection from the stub from getting back on the cable.

Is your cable getting longer everytime you add a transformer? What are your cable lengths? How wide are the steps?

One reference (Belden) shows Cat5 has about 3300 pF/km and a 67% velocity of propogation (VoP). Distance traveled times two (there and back) divided by the VoP gives the pulse width of the reflection step. There is another formula too that translates the impedance mismatch causing the reflection into the vertical step size but I don't have it off the top of my head. Google "Time domain reflectometer"



"It seems like I have passed the threshold (of putting too many transformers in parallel), and this has resulted in
a decrease of inductance and thus saturating the transformers. Is this an accurate read?"

Inductors in parallel increase the inductance.


Let us know how this works out.

 
Zap:
Wrong :
series L-s add, parallel L-s reduce the inductance

Lpar = 1/( 1/L1 +1/L2) as resistors. E.g. 100H and 50 Hy
in series = 150H, in parallel = 33.33 H





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