Determining wait-state

[jamesnguyen]

Hi everyone,

How do I determine the wait-state of the external flash memory to a processor (ADI blackfin). What characteristic of the CPU or external flash determine the wait-state? Thank you very much in advance!

James

 

[jamesnguyen]

Sorry. Please change "external flash" in my question to "external SDRAM".

 

[IRstuff]

Wait states are the states required for the processor to wait for the memory to put out valid data

TTFN

FAQ731-376

 

[MacGyverS2000]

This is answered in the memory's datasheet. If your processor's bus is slower than the memory's, you'll need to tack on the appropriate amount of delay time.

Dan - Owner

http://www.Hi-TecDesigns.com

 

[jamesnguyen]

Thank you all for your reply! What specific specifications am I looking for?

Are these numbers enough to determine the wait-state? If yes, how do I calculate it?

The processor core runs at 400 MHz
External bus interface runs at 80 MHz
SDR SDRAM's "cycle time" = 7.5ns

Best regards,
James

 

[zappedagain]

Dan,

Didn't you state that backwards? If the processor is faster than the memory then the processor will have to (insert) wait (states) until the memory is ready.

JN,

Pull up a datasheet for your memory. You'll see a timing diagram that will show you what parameters to watch for. You'll also see the same type of parameters in the processor datasheet (like Figure 11 and Figure 12 in the ADSP-BF534 datasheet). You need to make sure the processor isn't too fast for the memory; otherwise you'll need to add wait states.

John D

 

[IRstuff]

Is this for school?

TTFN

FAQ731-376

 

[jamesnguyen]

Thank you all again. I am not completely clear yet, but I at least I know what to look for now.

IRstuff:
Define "school". I am here to learn. If that's what what you call schooling, then yes, I am attending Eng-Tips school. I hope you understand that something which is obvious to you may not be obvious to other people. Just imagine what would happen if every question on this site is answered by "Is this for school?"

To answer your REAL question. No, this is for work.

Anyway, thank you.
James

 

[MacGyverS2000]

John,

Yeah, reverse that

Dan - Owner

http://www.Hi-TecDesigns.com

 

[VEBill]

If you're developing a new embedded system, then you should build a 'reference design' first (I assume they have a reference design). Get that working. Something simple, like an LED blinking. It'll be the best "several months more than expected" ever.

SDRAM interfaces have at least a dozen variables...

http://en.wikipedia.org/wiki/Synchronous_dynamic_random_access_memory#SDRAM_timing

By the time you're able to formulate a valid question, you could answer it yourself.

I started looking at RAM specs in order to upgrade an old PC. I learned a lot, but lost interest and bought a new PC. LOL.

 

[Noway2]

There is an additional factor that is frequently neglected when determining the bus speed: the loading effect from the number of devices attached to the bus. The more devices, the more capacitive load you have and the slower the rise and fall time of the lines on the bus and hence the slower it needs to operate as a cycle time.

If you are interested or think this may be an issue for you, Howard Johnson has a really good write up of this in his book High Speed Digital Design.