Kevin10
Electrical
- Aug 2, 2016
- 1
Hi,
When I debug ADS1247 chips, I find the problem:
AIN0 pin connects a capacitor to the ground. There are (AVDD + AVSS) / 2 bias voltage (2.5 V), as the negative input. AIN1 pins is as positive input. The datasheet of ADS1247 is
When AIN1 pin doesn't add bias voltage, the collection value is the same as the input signal. but when the pin combines with bias voltage. The acquisition value compared to the input signal reduces 3 times. I measure pin level directly with oscilloscope. If sine wave is peak to 2 v, the collection value after the conversion of peak value is only about 660 mv.
My application mode is AIN0 and AIN1 pins have the bias voltage. And then by blocking capacitance I input ac signal through AIN1 pin. Through the offset voltage it will be up to 2.5 V bias. Such a measured waveform is ±2 V.
Please help. Thank you!
When I debug ADS1247 chips, I find the problem:
AIN0 pin connects a capacitor to the ground. There are (AVDD + AVSS) / 2 bias voltage (2.5 V), as the negative input. AIN1 pins is as positive input. The datasheet of ADS1247 is
When AIN1 pin doesn't add bias voltage, the collection value is the same as the input signal. but when the pin combines with bias voltage. The acquisition value compared to the input signal reduces 3 times. I measure pin level directly with oscilloscope. If sine wave is peak to 2 v, the collection value after the conversion of peak value is only about 660 mv.
My application mode is AIN0 and AIN1 pins have the bias voltage. And then by blocking capacitance I input ac signal through AIN1 pin. Through the offset voltage it will be up to 2.5 V bias. Such a measured waveform is ±2 V.
Please help. Thank you!