15 MHz Clock Buffer / Level Translator

[jamesnguyen]

Hi,
I have an AC clipped sine clock with an amplitude of 1Vpp @ 15 MHz. I need to convert this signal to a TTL-compatible signal. What's the best way to do this?

Regards,
James

 

[VEBill]

Perhaps a zero-crossing detector, one with a TTL-compatible output.

 

[jamesnguyen]

What's about using a unbuffered inverter with a feedback resistor?

 

[VEBill]

The "1Vpp" at its highest peak (i.e. +0.5 volt) is still a logic zero for most gates.

There are a half-dozen ways to increase the amplitude using analog circuitry. But that would be the last resort.

Perhaps a simple comparator with 0v as the reference?

Here's a tech note that might be useful (slow stuff at the top, higher speeds towards the bottom):

http://sound.westhost.com/appnotes/an005.htm

 

[jamesnguyen]

I could remove a DC blocking capacitor at the clock source to get a 1V DC offset (highest voltage = 1.5V, lowest voltage = 0.5V). With this, I am thinking of using a level converter to translate to a TTL level.

James

 

[VEBill]

That sort of approach might work.

For reliability, it's best to have the signal sitting 'fat and pretty' well into the specified voltage bands for each logic level (for the chosen gate's input). In other words, make sure the circuit keeps on working even if things drift a bit (perhaps with temperature, EMI or age). What you don't want is a solution that just barely works.