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I need to bit bang a JTAG interface and I'm not sure how to do it. The JTAG signals are connected to I/Os on a FPGA. I have downloaded the JTAG spec and am having troubles wading through it. The chip I'm programming is a clock generator. Not the same one I asked questions about earlier this...

I have the following clock requirements for my present design: 200 MHz LVDS 166 MHz LVDS 166 MHz LVDS 166 MHz LVCMOS 166 MHz LVCMOS 166 MHz LVCMOS 166 MHz LVCMOS 150 MHz LVDS 150 MHz LVDS 133 MHz LVDS 133 MHz LVDS 100 MHz LVCMOS 100 MHz LVCMOS Multiple clocks on single ended and differential...