As the semiconductor industry races to keep pace with Moore’s Law, which regards the doubling of transistors per square inch on integrated circuits, lithography hardware systems are not always able to provide a quality image for creating circuits. Fortunately, software developers have created tools that can play certain tricks on these images, to create reasonable-quality images with existing hardware.
Multi-patterning is a new approach that enables accurate lithographic resolution at today's most advanced nodes. In this five-page white paper, you will learn:
Why advanced process nodes need multi-patterning
The role multi-patterning plays, compared to advanced lithographic systems
What different types of multi-patterning the industry can expect to see
About the Author:
David Abercrombie is the advanced physical verification methodology program manager at Mentor Graphics. For the last few years, he has been driving development of EDA tools that can solve the issues in design to process interactions (DFM) that create ever-increasing yield problems. David received his BSEE from Clemson University, and his MSEE from North Carolina State University.
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