Contact US

Log In

Come Join Us!

Are you an
Engineering professional?
Join Eng-Tips Forums!
  • Talk With Other Members
  • Be Notified Of Responses
    To Your Posts
  • Keyword Search
  • One-Click Access To Your
    Favorite Forums
  • Automated Signatures
    On Your Posts
  • Best Of All, It's Free!

*Eng-Tips's functionality depends on members receiving e-mail. By joining you are opting in to receive e-mail.

Posting Guidelines

Promoting, selling, recruiting, coursework and thesis posting is forbidden.

Students Click Here

White Paper: Improving Design Reliability by Avoiding Electrical Overstress

Engineers will note that when electronics fail, electrical overstress (EOS) is typically the cause.

As integrated circuit (IC) designs become more complex, they will continue to use multiple voltages, which will increase the risk of EOS.

In this 5-page white paper you will learn:
  • How EOS occurs and how it can affect an IC
  • The importance of understanding pin voltages
  • How design technology such as CALIBRE PERC can help prevent EOS

About the Author:
Matthew Hogan is a product marketing manager at Mentor Graphics with over 20 years of experience in the industry.

He has also served as a Member of the Board of Directors at the EOS/ESD Association, and as a senior applications engineer at Mentor Technologies.

Complete the form on this page to download your free white paper. Your download is sponsored by Mentor Graphics.

Get Your Resource

Please provide the following to access your download.

Close Box

Join Eng-Tips® Today!

Join your peers on the Internet's largest technical engineering professional community.
It's easy to join and it's free.

Here's Why Members Love Eng-Tips Forums:

Register now while it's still free!

Already a member? Close this window and log in.

Join Us             Close