Catapult High-Level Synthesis (HLS) is hot in markets like Deep Learning/AI, Computer Vision, Communication (5G, IoT), and Video, just to name a few. Designing at the C++ or SystemC-level with a fast path to highest QofR (performance, area and power) for both FPGA and ASIC.

Catapult’s ecosystem is more than just “C to RTL”, with HLS-aware code and functional coverage similar to System Verilog, and formal equivalence checking, enabling competitive differentiation and accelerated time-to-market. Having a complete low-power methodology from block to SoC whether starting from C or RTL with PowerPro is also critical in emerging ultra-low-power sensitive markets.

This resource will help you find key sessions-panels at DAC from researchers, customers, and our expert technologists; and various resources detailing the recent innovations in HLS, Verification, and RTL Low-Power since DAC 2019.

To download, please complete the form on this page. Your download is sponsored by Mentor, a Siemens Business.