Recent content by mmracing

Jack, Another engineer actually took up this cause. It is pretty interesting. The other engineer actually has something finished but I haven't been able to try it out. Stay in touch and I'll let you know what I find. gf

logbook, The bright spark comment is pretty funny. I'll send residuals to you every time I use it. ;-) Someone at my work gave me the JTAG spec. If interested I'll send it to you. macgyver, I guess the name says it all. That is a great link and I intend on reading it right away. BTW...

That is pretty cool and I'll definitely file that away. But I need to embed the JTAG stuff. Meaning that I have access to the JTAG signals through a FPGA in my design. By bit-banging the JTAG signals through embedded software I can load a new profile in the clock synthesizer (sp?) on the...

I have a programmer for it also. You're right that I want to embed so that we can change frequencies of this clock synthesizer on the fly. I think it's a little weird but that's what design wants to do. I started reading the spec and some other literature and I think I can do it. But I was...

I need to bit bang a JTAG interface and I'm not sure how to do it. The JTAG signals are connected to I/Os on a FPGA. I have downloaded the JTAG spec and am having troubles wading through it. The chip I'm programming is a clock generator. Not the same one I asked questions about earlier this...

Thanks for the help fellas. I'm in the process of looking at On Semis web-site and you're right that they have a lot of good stuff. I got a response from IDT last night with a 5 chip solution. 2 clock generators and 3 distribution chips. It would be nice to do this with 1 or 2 chips but...

I'll check them out. Because I have multiple places that need the same clock frequency.

I have the following clock requirements for my present design: 200 MHz LVDS 166 MHz LVDS 166 MHz LVDS 166 MHz LVCMOS 166 MHz LVCMOS 166 MHz LVCMOS 166 MHz LVCMOS 150 MHz LVDS 150 MHz LVDS 133 MHz LVDS 133 MHz LVDS 100 MHz LVCMOS 100 MHz LVCMOS Multiple clocks on single ended and differential...