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Recent content by JeffJackson

  1. JeffJackson

    Old Xilinx fault code

    Hi all, Just wondered if anyone can recall the old fault code generated by Xilinx when mapping and fpga. Using a XC4020HQ208, design simulates and compiles with no errors. When building I get NGDBUILD done then when mapping the following: ERROR:OldMap:928 - There is no signal on pin A0 of CY4...
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