Sampling rate is min 500Hz..... I was thinking that of the clock frequency is too high, signals may not be latched accurately. Do you guys have any circuit for overranged detection?
hi... got a question guys... i am working on a 16-bit ADC IC to convert analog signals of low amplitude and frequency. I am goin to use the dual-slope architecture. After some calculations, i discovered that the frequency of the clock needed is too high (MHZ)...So the idea is working on 8 bits...
