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Low SNR PLL

Low SNR PLL

Low SNR PLL

(OP)
I need to develop a digital phaselock loop to track a very low SNR quadraphase signal.  The Esym/No is around 0.5 dB and there is a lot of doppler (1kHz/sec change for a 32 ksym/sec modulation rate).  I have seen smoothers and Kalman-type approaches and they are pretty complicated and I need to put several of these demods in my receiver to handle multiple received signals from different users.

I am about 1.5 dB below where a reqular Costas-type PI Loop fails, so I am sure I need to increase my loop SNR by using memory (like a smoother) but want a simple approach that will let me open up my loop bandwidth and still track well.

Any suggestions??

RE: Low SNR PLL

This post is so outside my field of expertise but it such an interesting post I wanted to respond.

1) Is there any way to additionally band limit the incomming signal to reject out of band noise?

2)Is there anything regular about the doppler slewing that is peridic that can be rejected through disturbance tracking/cancellation?

3) Seek University consultation on the problem.

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