designing a DAC
designing a DAC
(OP)
I need to design a DAC for a work experience project and i hope someone can help, it is an 11 bit DAC, but here is the problem:
D to A function
The D to A function is not binary weighted across all 11 bits. That is a true 11 bit DAC would have 2^11 sates (2048), where as this 11 bit DAC has 127 states, that is 7 bits. The tables below try to explain this.
Segment D0 D1 D2 D3 D4-0 D4-1 D4-2 D4-3 D4-4 D4-5 D4-6
Weight 1 2 3 4 16 16 16 16 16 16 16
(Example)
State 58
Segment D0 D1 D2 D3 D4-0 D4-1 D4-2 D4-3 D4-4 D4-5 D4-6
Weight off on off on off off off on on on off
The first block shows the 11 bits with their respective title. Underneath we see the corresponding “weight”. As one can see the first 4 bits are binary weighted, however the final 7 bits all have a weighting of 16. The remaining boxes show what bits are high for specific weight. Therefore it is not as straightforward as placing an 11-bit DAC on the test board as the output weighted values would not be correct.
Any suggestions, thanks in advance.
D to A function
The D to A function is not binary weighted across all 11 bits. That is a true 11 bit DAC would have 2^11 sates (2048), where as this 11 bit DAC has 127 states, that is 7 bits. The tables below try to explain this.
Segment D0 D1 D2 D3 D4-0 D4-1 D4-2 D4-3 D4-4 D4-5 D4-6
Weight 1 2 3 4 16 16 16 16 16 16 16
(Example)
State 58
Segment D0 D1 D2 D3 D4-0 D4-1 D4-2 D4-3 D4-4 D4-5 D4-6
Weight off on off on off off off on on on off
The first block shows the 11 bits with their respective title. Underneath we see the corresponding “weight”. As one can see the first 4 bits are binary weighted, however the final 7 bits all have a weighting of 16. The remaining boxes show what bits are high for specific weight. Therefore it is not as straightforward as placing an 11-bit DAC on the test board as the output weighted values would not be correct.
Any suggestions, thanks in advance.





RE: designing a DAC
Or have I misunderstood something ?
RE: designing a DAC
RE: designing a DAC
If you really want that kind of response then I suggest a four-bit DAC with regular binary weighting (1-2-4-8), plus a seven bit latch with each output sourcing a current of weight-16. These outputs could then all be summed by an op-amp. BUT it may be better to have successive summing stages, i.e. one op-amp for the binary outputs, one which sums the 16-weight outputs, and a final one which sums both. That way you can trim the individual gains more easily.
RE: designing a DAC
RE: designing a DAC
TTFN
RE: designing a DAC
It would be very helpful if ye could go into more detail as to how i could get the output weighted vaslues to be correct.
RE: designing a DAC
Depending on the accuracy you require you don't need a special D-A chip; you can make a reasonable D-A out of latches with different values resistors into the op amp summing junction. If you use CMOS latches to give a good logic "1" level of close to +5V, provided the resistor currents are not too large (say 100uA steps, rather than 1mA) you can get quite good results this way.
As currents are summed at the op-amp - remember that the input is a "virtual ground", assuming 5V available from the latch o/p then Ohms Law gives the value of each resistor, e.g. 50K, 25K, 12.5k 6.25K, making the 16-weight value 3.125K.
All you then need to decide is the value of feedback resistor at the op-amp to get the scale maximum voltage required, e.g. 3.9k will give approx 5V full scale.
Hope that helps!
RE: designing a DAC