frecuency stability(PPM) in a PLL
frecuency stability(PPM) in a PLL
(OP)
Hello, my name is David.I`d like to know if the frecuency stability of the output signal in a PLL is the same as in the clock reference used in the loop.I mean, if the reference clock is 4 PPM, and the PLL has a multilplicative factor x15 to obtain a 300 MHZ output signal, has this output signal also a frecuency stablity of 4PPM?does the PLL only make the phase noise of the output signal get worse?
I`ll be deligthed to know any link to application notes or articles related with this toipic.
Tanks in advance
I`ll be deligthed to know any link to application notes or articles related with this toipic.
Tanks in advance





RE: frecuency stability(PPM) in a PLL
There is a lot of data articles, etc. search e.g.
<www.dogpile.com>
<nbucska@pcperipherals.com>
RE: frecuency stability(PPM) in a PLL
thanks again.
RE: frecuency stability(PPM) in a PLL
Search <www.dogpile.com> or <www.google.com> or
<www.yahoo.com> for PLL or phaselock.
or <www.ti.com> or <www.onsemi.com> or <www.fairchildsemi.com> appl.notes for PLL. Or
get from <www.amazon.com> Floyd Martin Gardner's
book about "Phaselock techniques"
===============OR===================
Do you have a specific problem?
<nbucska@pcperipherals.com>
RE: frecuency stability(PPM) in a PLL
RE: frecuency stability(PPM) in a PLL
I hope this could help you to better understand my problem.
Thanks for your former answer, by the moment I'll try with last links you told me.
AREVALO
RE: frecuency stability(PPM) in a PLL
AVERAGE of the phase error. Averaging == low pass filtering.
The frequency stability of the clock is a two edges sworld:
It may increase the max. frequency usable but generates more
noise.
<nbucska@pcperipherals.com>