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Externally summed CTs for bus protection
3

Externally summed CTs for bus protection

Externally summed CTs for bus protection

(OP)
Starting this not to steer off another thread, but I inquire 2 questions:

1. At what point or fault levels do engineers typically move away from externally summed CTs for (over-current) bus differential protection? C800 class CTs of concern here FWIW.

2. Can externally summed bus protection CTs be used in networked circuits?

RE: Externally summed CTs for bus protection

About a decade ago... winky smile

There's at least a couple of way of interpreting that question. If you're using an overcurrent relay as a bus differential, everything is summed external to the relay, so that may not really be what the question is.

If you're talking a differential relay that produces restraint and operate currents, either electrically or numerically, you have to be careful what you sum up externally. You need to have every source on its own CT but you can parallel up loads. The problem with paralleling a source and a load is that for an external fault on that load circuit your restraint current will be much lower than it would be if every CT had its own input. Throw in a bit of error, and that missing restraint current may be allow the relay to operate for an external fault.

RE: Externally summed CTs for bus protection

(OP)
Basically using an over current relay (351) for bus protection vs using a B90 or 487B. The over current approach is much simpler and I've seen it used extensively on distribution buses- but I am wondering at what point it begins to have its limitations.

RE: Externally summed CTs for bus protection

That's essentially a low impedance version of the high impedance bus diff. For my liking, we still have far too of them. But for that application all CTs are summed external to the relay, so I'm not sure what the original question is asking. If it's all currents summed into an overcurrent relay vs. a low impedance bus diff I'll stick with my original answer of about a decade ago. It's not something I'd even consider today.

RE: Externally summed CTs for bus protection

(OP)
But why the choice of a low impedance bus differential relay over an over-current relay? Why the switch? My apologies for not being clear about this in the first post.

RE: Externally summed CTs for bus protection

If the choice is a low cost EM overcurrent vs. a higher cost EM differential and there aren't going to be performance issues then the EM overcurrent makes sense, in that environment. Those were the "well, it reclosed, everything's ok" days. Now we have a compliance obligation to know that every operation is correct. There's also been a transition from (before my time) where stuff seemed to be expensive and personnel time inexpensive to where stuff is less expensive and personnel time is more expensive. So if a more expensive relay requires less time figure out what happened that's a good thing.

That may be a bit simplified, but 20 years ago we'd pick just the "right" relay for the application and have lots of different relays to purchase, design around, and maintain spares for. Now it's believe to be less costly to have as few different designs as possible and some applications get a design that would have been considered gross overkill 20 years ago. Part of it is compliance obligations, part of it is simply trying to get more out of each protection engineer than 20 years ago and there's no time to "optimize" each design, nor do we see the point.

I'd much prefer to get really good at a handful of standard designs, portions of which may be omitted at any given location, than to come up with just the right design every time.

So, if I need a full out low impedance bus diff design I see absolutely no value in also having an overcurrent based design. Would an overcurrent relay work some places? Sure, undoubtedly; but the savings would be illusionary.

RE: Externally summed CTs for bus protection

If by externally summed, you mean connecting the CTs in summation external to a current relay; the problem is the lack of restraint for through faults. The answer then is: when you don't want to trip for through faults, use a multiple input, muti-restraint low impedance bus differential relay. The other option is to use a high impedance relay.

RE: Externally summed CTs for bus protection

I am replacing a mechanical high impedance relay with a low impedance microprocessor in a project I am currently working on. The comment was that I was given to not worry about CT saturation for external faults was that SEL's CT saturation restraint algorithm will prevent external fault tripping. I am not sure what to say about that. For event analysis, it is nice to see all the currents but I don't know how much I should be trusting an algorithm for blocking out of zone tripping. If we just used a high impedance diff relay, we wouldn't have to rely on an algorithm to prevent out of zone tripping. The high imp relay would guard it by design.

RE: Externally summed CTs for bus protection

(OP)
@David: But nothing beats the elegance of simplicity :) In my case it will simply be two more feeder over current relays. The 487b will actually be a departure from the feeder relays. Although I do agree and very well put as per usual. However, I am also looking at this from an electrical theory perspective related to performance. I've been told that one of the down sides to over current buss differential is that when a feeder faults, the faulted feeder CT is far more likely saturate and inadvertently trip, however I do not know to what extent or what fault current levels this is more likely to happen? My understanding is that all low impedance designs are prone to saturation, just one handles it with logic. Or am I wrong?

RE: Externally summed CTs for bus protection

(OP)

Quote (HamburgerHelper)

I am replacing a mechanical high impedance relay with a low impedance microprocessor in a project I am currently working on. The comment was that I was given to not worry about CT saturation for external faults was that SEL's CT saturation restraint algorithm will prevent external fault tripping. I am not sure what to say about that. For event analysis, it is nice to see all the currents but I don't know how much I should be trusting an algorithm for blocking out of zone tripping. If we just used a high impedance diff relay, we wouldn't have to rely on an algorithm to prevent out of zone tripping. The high imp relay would guard it by design.


Being SEL I am sure you will get your moneys worth. Unless you are dealing with profound saturation the relay should restrain on external faults but trip immediately on internal ones. However, FWIW I do know of utilities that have modernized their relaying from EM to microprocessor but kept the high impedance bus protection. Here is one example of a paper by SEL where a utility actually chooses electromechanical relays for bus protection despite replacing everything else. See page 10, descriptions numbered 2 and 7:

https://cdn.selinc.com/assets/Literature/Publicati...

RE: Externally summed CTs for bus protection

Not knowing the application, and assuming it might be in switchgear, high speed might be of a concern. In that case, an over current might be too slow.

There are papers on the advantages of both low and high impedance relays, and the answer is it depends on you, your application, your people who work on it, etc.

RE: Externally summed CTs for bus protection

(OP)
No gear, just outdoor bus work.

RE: Externally summed CTs for bus protection

When a CT saturates, it produces less than the ratio current; so overcurrent tripping is less likely not more. False differential operate current can result, but you'll be restrained by the quantities from the other feeders. The slope is set-able by the user. Work through the instruction book example to see if saturation is a concern.

RE: Externally summed CTs for bus protection

(OP)
Which instruction book though? ponder

My understanding is that when a CT produces less current, there is less current to cancel out the current coming from all of the other feeders combined. Ie, if bays 1-9 produce 90 amps and the saturated bay CT only produces 80 from saturation, 10 amps will flow through the relay when in theory it would be close to zero for a none saturated CT.

RE: Externally summed CTs for bus protection

One of the advantages of the high impedance differential is that the other CT's will force current through a saturating CT, instead of the high impedance associated with the relay.

If you expect that under some cases you will see error current, that should be taken into account in your calculations, such as slope or setting.

RE: Externally summed CTs for bus protection

Mbrooke,

I see SEL is now referencing IEEE C37.110. See the CT Requirements section of the 487B-1 manual. Looks like they may have a program available as well.

Your understanding is correct. With a low impedance relay, all currents flow into the relay and the differential current is summed in the relay. The input currents are used for restraint. As cranky said, you can set your slope (Iop/Irt) to allow for the 10 amps of Iop in your example.

RE: Externally summed CTs for bus protection

(OP)
@stevenal thank you and I will check that out. :)

But what should I consider in setting if I do not have restraint current?

RE: Externally summed CTs for bus protection

I suppose you may be able to simulate your system and CTs so you could find a suitable pickup setting, but it is not an approach I would recommend. If you wish to parallel CTs, suggest going high impedance.

RE: Externally summed CTs for bus protection

(OP)
So basically the recommendation from the most experienced is either a high impedance relay (587Z) or a numerically summed low impedance relay (487B).


Question. In places where saturation is unlikely (such as a distribution bus with 1200/5 C800 CTs 10,000amp and under short circuit) is over current differential protection still ill advised?

RE: Externally summed CTs for bus protection

Quote (MBrook)

Question. In places where saturation is unlikely (such as a distribution bus with 1200/5 C800 CTs 10,000amp and under short circuit) is over current differential protection still ill advised?
You need to look at the burden and the system X/R ratio as well as the fault current to determine saturation.
Vs = (1+X/R)·If·Zb
I would recommend low impedance with restraint or high impedance. If you are concerned about cost, consider a fast-bus trip scheme instead of bus differential. If you have microprocessor relays on the main, bus tie, and feeders, you might achieve 3 cycle operation without any additional relays or CTs.

RE: Externally summed CTs for bus protection

Our local DisCo had adapted the fast bus trip scheme for new installations. Previously a High Z (GE PVD) scheme was used. SEL has a nice explanation of the scheme in the 251 Manual, along with a scheme that allows the bus relay to handle a failed feeder relay, or a feeder relay OOS for other reasons. There is a bit of wiring involved, so this is on new relay panels / switchgear.

I can confirm from commissioning these schemes, the 3 cycle time (between relays) is easily achieved.

RE: Externally summed CTs for bus protection

After my adventures of the past few days I am so terribly glad that our dabbling in the 251/251C fast bus scheme was a brief episode and that we've long since moved into a more enlightened era of dual feeder relays, bus protection, breaker failure logic, and a maintenance mode switch on the transformer protection. It's all been SEL from then till now, but that fast bus trip era was truly a misguided, penny wise pound foolish, attempt at getting more that what you were willing to pay for. SEL had this great idea how you could get more out of fewer relays; they sold fewer relays and we got worse results over the long run. There's no free lunch.

That scheme has some obvious advantages and it was well sold; but that was 20 years ago. There are some very subtle ways for it to fail; at the moment I don't feel that sharing would be appropriate but it seems to have built in several traps. Don't (just) look at first cost; look at the costs (both tangible and non-tangible) of an extended outage simply because some corner case behaves radically differently from what everybody is more familiar with.

RE: Externally summed CTs for bus protection

(OP)

Quote (jghrist)

You need to look at the burden and the system X/R ratio as well as the fault current to determine saturation.
Vs = (1+X/R)·If·Zb
I would recommend low impedance with restraint or high impedance. If you are concerned about cost, consider a fast-bus trip scheme instead of bus differential. If you have microprocessor relays on the main, bus tie, and feeders, you might achieve 3 cycle operation without any additional relays or CTs.


I know long runs in the CT circuit (higher ohms) decrease saturation, but, how does low burden play into this?


Quote (David Beach)

After my adventures of the past few days I am so terribly glad that our dabbling in the 251/251C fast bus scheme was a brief episode and that we've long since moved into a more enlightened era of dual feeder relays, bus protection, breaker failure logic, and a maintenance mode switch on the transformer protection. It's all been SEL from then till now, but that fast bus trip era was truly a misguided, penny wise pound foolish, attempt at getting more that what you were willing to pay for. SEL had this great idea how you could get more out of fewer relays; they sold fewer relays and we got worse results over the long run. There's no free lunch.

That scheme has some obvious advantages and it was well sold; but that was 20 years ago. There are some very subtle ways for it to fail; at the moment I don't feel that sharing would be appropriate but it seems to have built in several traps. Don't (just) look at first cost; look at the costs (both tangible and non-tangible) of an extended outage simply because some corner case behaves radically differently from what everybody is more familiar with.

Thanks, a wealth of wisdom as pure usual :) Considering your experience, practicality and advanced knowledge in the field of protective relaying I am going to take your word on fast-bus. Having decentralized bus bar protection for 12kv and above has never sat right with me, I actually prefer having more relays.

If you feel comfortable saying, what do you use for bus protection at the 12-34.5kv levels?

RE: Externally summed CTs for bus protection

At that level we're using the 587Z plus optical arc flash detection plus a maintenance mode switch on the transformer protection. We go that route in part because some switchgear would require three 487Bs, one per phase, to cover the 8 or 9 breakers and there's no place to mount all of those. Anything transmission gets redundant 487Bs.

RE: Externally summed CTs for bus protection

(OP)
Sounds like a well thought out practice. :) On the 487Bs, you've never had any inadvertent operation from saturated CTs, correct?

RE: Externally summed CTs for bus protection

David, nice comments.

The problem with that scheme with the 251 is that it keeps cropping up as a way to save money.

What I don't find is papers on how to best install the fibers for arc-flash protection.

RE: Externally summed CTs for bus protection

I can't recall any misoperations of a 487B, neither over tripping nor under tripping, on our system

RE: Externally summed CTs for bus protection

Quote (Mbrooke)

I know long runs in the CT circuit (higher ohms) decrease saturation

Make that increase.

RE: Externally summed CTs for bus protection

(OP)
Ok, guess I need a course on factors increasing CT saturation. Any good links or papers on the subject?

RE: Externally summed CTs for bus protection

Stan Zochall's CT book available from SEL would be a good start.

RE: Externally summed CTs for bus protection

(OP)
Also anyone know how to find the line angle on a distribution bus?

RE: Externally summed CTs for bus protection

Third book on https://selinc.com/publications/bookstore/

Appears to also be available through Amazon.

Why would you need a "line angle" for a bus? I imagine that you could calculate the impedance as though the bus were a line and use that. Pretty sure you'll get something over 80 degrees.

RE: Externally summed CTs for bus protection

(OP)
The first paper makes not of line angles and CT saturation on page 3, which threw me off.

RE: Externally summed CTs for bus protection

(OP)
And oh, thank you for the link. Much appreciated :)

RE: Externally summed CTs for bus protection

I also suggest IEEE C37.110.

RE: Externally summed CTs for bus protection

You can calculate X/R from the line angle. You need the fault current in complex form to get X/R or the line angle. Line angle = arctan (reactive part of fault current / real part of fault current). X/R = tan ( line angle). For a distribution bus on the load side of a power transformer, the X/R ratio is high because most of the fault impedance is the transformer which has a high X/R ratio.

RE: Externally summed CTs for bus protection

(OP)
I take it 3 paralleled 30/40/50 MVA 115-34.5kv transformers will produce a very, very high line angle?

RE: Externally summed CTs for bus protection

Yes. Hopefully you should be able to get the fault X/R from your system model by applying a 3LG fault on the bus.

RE: Externally summed CTs for bus protection

(OP)
I have the transformer R and X for each unit, plus the source 115kv impedance. Will this be enough?

RE: Externally summed CTs for bus protection

Quote (MBrooke)

I have the transformer R and X for each unit, plus the source 115kv impedance. Will this be enough?
Yes, if you have the complex 115 kV impedance. Combine the 3 parallel transformer impedances, add to the 115 kV impedance to get the total impedance. Ztotal = Z115 + 1/(1/Zt1 + 1/Zt2 + 1/Zt3) All Zs are complex (R + jX).

RE: Externally summed CTs for bus protection

(OP)
Thanks. :) But I will be frank, it seems CTs saturate a lot more than I expected at distribution busses- perhaps more so than transmission.

RE: Externally summed CTs for bus protection

(OP)
One last question. Why is it that a higher CT circuit resistance increases saturation? My understanding has been that a higher resistance impedes current, and less secondary current means less flux in the core needing to offset that being taken out... similar to overloading a transformer... Or am I off? In short I have always assumed higher resistance means less saturation.

RE: Externally summed CTs for bus protection

The more the impedance on the CT circuit, the higher the voltage the CT must generate to push the same current through the circuit.

You should keep the impedance low to prevent saturation of the CT.

Except in the high impedance differential.

RE: Externally summed CTs for bus protection

(OP)
Thank you and I will do that.


Once I have CT saturation values and other parameters, should I let them extensively dictate my 487B settings or be more casual? I heard a member mention on here that the 487B makes a trip decision before saturation can take place?

RE: Externally summed CTs for bus protection

I just try to keep the voltage below 50% of the effective C rating. Effective means it has been adjusted for the tap used.

The problem with saturation is not failure to trip, it is the possibility of tripping for out of zone faults. Tripping decision speed doesn't come into play, since it can still make the wrong decision on the very next processing interval, or the next.

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