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cause of AND gate breaking

cause of AND gate breaking

(OP)
Id like a second option on this just because its for an established product.

We have an ultrasound medical iamging device which has a motor attached to it. The motor is a galil controller. The galil controller issues triggers via a 3V high off signal which is converted to 0V for the trigger. The signal which recieves the trigger keeps breaking. It could also be that a test execuationer for the board hooked up the boards wrong too though.

The reason the doppler imgign modlues failed is that trigger input (pin 2) from the galil controller to IC U54 (AND gate) was grounded. Upon removing the AND gate, the short circuit went away, showing it was broken. A schematic is as follows
http://files.engineering.com/getfile.aspx?folder=6...

The input from the galil motion control is labeled as ‘pulse trigger’. The Doppler select is a signal which is high for ultrasound imaging and then low for Doppler imaging, it is a 5V signal when on which has little ripple or noise. Im not even sure in what state the chips are breakign in.

The chips that is breaking is IC U54 which and has a description as follows. Part number: FAIRCHILD 74AC08SC (IC Gate and Quad 2-Input AND gate 14-SOIC). The 74AC designated high speed CMOS. The pinout for the device is as follows74AC08SC (IC Gate and Quad 2-Input AND gate 14-SOIC).



The galil trigger signal that is going into the pin 2 is shown below. It is a normally off at a 3V high signal that turns on for a trigger pulse of 0V for 600ns at 0V. There is likely some overshoot on the negative pulse although the image below will also show RF induced noise too. The following image as taken with the probe touching pin 2 and the probe in an erroneous state (it completes one image sequence movement before erroring out). There is probably inducatance is the approximat,ly 10ft of cable which the galil signal passes through.
http://files.engineering.com/getfile.aspx?folder=b...


From the 74AC08SC datasheet, the minimum voltage the pin can withstand is -0.5V. It is likely we are below this value at the lowest voltages. Another likely event is that if someone plugs the image pulse into this connector, it will also break the gate by exceeding the VCC+0.5V rating. The supply voltage (VCC) was a flat, contast 5V and is unlikely to be the issue.
https://www.fairchildsemi.com/ds/74/74ACT08.pdf


An example of another IC in the console that handles a galil trigger is the SN74LS123N in a different module, this is a IC- Dual Monostable Multivibrator. I have no record of this chip ever breaking in our consoles and it handles the same signal as the pulse that breaks. I cant seem to find hte low voltages it can withstand in the datasheet.


Anyone have any ideas, does the write up seem logical?
What about ways to fix it. A capactior across the output with a time constant between the ripple of overshoot and that of the main pulse. How about a fast acting diode at around 0V? A replacment for AND gate that is more robust. I believe the galil pulse is fixed.

RE: cause of AND gate breaking

The 0.5V over/under spec is simply to prevent excess current from going through the ESD clamp diodes in the chip. These diodes can easily survive sub-microsecond pulses of several hundred volts. The LS123 has a similar ESD clamp structure, so its characteristics should be similar. HOWEVER, the LS123 is a Schottky TTL device, while the ACT08 is a CMOS device.

I would suggest that someone who understands the ACT08 a little better do some failure analysis to determine how the parts are "breaking." If the failures are similar, then one can being to hypothesize the root cause. TTL devices are slightly less susceptible to ESD than CMOS, so that's a strong candidate, particularly if you're in the US in the winter. These parts are typically only rated to survive ~2kV ESD pulses, although they typically can handle more.

TTFN
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RE: cause of AND gate breaking

CMOS devices can enter destructive latch-up if the input voltage exceeds the supply voltage. This is because a parasitic diode is formed in the device substrate which short-circuits the power supply rail, the high current then causes the device to fail. Joining different pieces of equipment together directly is not good practice: different ground potentials can exist which spoil your supposed '0V' connection and cause unintended noise on top of the real signal into the logic input. One proper way to avoid that problem is to use opto-isolator devices between the different systems, however your pulse is a bit narrow for the average opto device. If this solution is not possible, to fix your repeatedly failing gate, as it's CMOS you could try a series resistor of around 1K without upsetting the inpt pulse significantly. This may limit any overvoltage enough to prevent latch-up.

RE: cause of AND gate breaking

(OP)
thanks again everyone.

I think that we have some understand of this but im going to do a different post for some help on this to the new point that we are at.

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