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Problem understanding connecting power and logic ground in schematic

Problem understanding connecting power and logic ground in schematic

(OP)
Hi all,

I'm designing V2 of a PCB that uses a TI TPS6102x boost converter (http://www.ti.com/lit/ds/symlink/tps61020.pdf).  I don't understand the schematic concerning the logic ground and power ground.  All the caps and R2 are tied to PGND while PS and GND are tied to power ground.  What's the purpose of separating these grounds in the chip but then tying them together in the PCB?  Am I misunderstanding something?
 

-Russ

RE: Problem understanding connecting power and logic ground in schematic

You need yo consider the resistance of the tiny conductors inside the chip. The conductors cannot be made arbitrarily wide or thick.
If PG and SG were tied together inside the chip, there would be interaction betwee voltage drop in the PG, aka ground noise, and the SG. Keeping them separate until they meet solid copper outside the chip avoids that problem.

Sometimes, there are several SG pins available around the chip and it is good education to measure resistance between them. You will find that it isn't zero ohms.

For HF applications, also inductivity plays a role.

Gunnar Englund
www.gke.org
--------------------------------------
Half full - Half empty? I don't mind. It's what in it that counts.

RE: Problem understanding connecting power and logic ground in schematic

This thing clocks 600kHz, and the number one problem with IC package leads is the inductance.  Since one would not want the digital switching currents inducing voltages on the analog ground, the digital and analog grounds are separated on the IC.  Once everything has made it through the lead inductances, the grounds can be connected back together again.

TTFN
FAQ731-376: Eng-Tips.com Forum Policies

RE: Problem understanding connecting power and logic ground in schematic

(OP)
Thanks so much for the explanations.  The message I take from this is that I can tie PS, GND, and PGND together near the chip and connect all other components to this single ground bus.  Please correct me if I'm wrong or oversimplifying.

-Russ

RE: Problem understanding connecting power and logic ground in schematic

As long as you don't consider a sheet of copper on the PCB as a guaranteed 0V reference plane, sure.  How much noise are you willing to accept on that plane?  How will noise on that plane affect surrounding components?  And so on...

Dan - Owner
http://www.Hi-TecDesigns.com

RE: Problem understanding connecting power and logic ground in schematic

(OP)
Thanks Dan.  This serious EE stuff is, shall we say, challenging to me.  The only components I have that I think might have noise sensitivity are an Atmel ATmega 328P and an XBee radio.  The ATmega has its AREF tied to ground via 0.01 uF cap.  I don't use the ADC, so its pins are tied to Vcc.  Vcc on the Xbee has 1 uF and 8.2 pF caps tied to ground, per Digi's spec.

If I can ask one closely related question: is it recommended to have a copper pour on this PCB?  If so, should it be localized or on one or both sides of this 2-layer PCB?  There are components on both sides.

-Russ

RE: Problem understanding connecting power and logic ground in schematic

Copper serves multiple purposes on a board, both as pute conductors and as electromagnetic shielding.  In some cases, it also serves to remove or spread heat from hot components.  It should not be unusual to see a single layer of a board solely devoted to the ground plane.

TTFN
FAQ731-376: Eng-Tips.com Forum Policies

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