GND plane vs. ESD protection choice
GND plane vs. ESD protection choice
(OP)
Hi -
I'm in the final stages of the Datalogger design for cars. I had originally wanted to include clamping diodes on all the analog inputs, using the PACDN017 smd array from CalMicro.
http://www.calmicro.com/products/data/pdf/pac_dn017.pdf
After much pushing and shoving in the PCB layout, there is room, finally. Unfortunately, it would only be on the bottom layer - simply no room on the top layer.
Given that all the other components are SMD, the GND plane below the analog section is nice and almost unbroken. Good for analog signals :) If I add in this ESD array on the bottom, it chops that GND plane up but good.
So the question is, which is more important for a vehicle application ? Nice smooth GND plane, or ESD clamping diodes for each input ?
Dean.
I'm in the final stages of the Datalogger design for cars. I had originally wanted to include clamping diodes on all the analog inputs, using the PACDN017 smd array from CalMicro.
http://www.calmicro.com/products/data/pdf/pac_dn017.pdf
After much pushing and shoving in the PCB layout, there is room, finally. Unfortunately, it would only be on the bottom layer - simply no room on the top layer.
Given that all the other components are SMD, the GND plane below the analog section is nice and almost unbroken. Good for analog signals :) If I add in this ESD array on the bottom, it chops that GND plane up but good.
So the question is, which is more important for a vehicle application ? Nice smooth GND plane, or ESD clamping diodes for each input ?
Dean.





RE: GND plane vs. ESD protection choice
If your ground plane gets segmented up, esp under your micro, you are asking for trouble. Ground return current is probably the most neglected current. Allow for the current in the ground to follow the same path as the supply current. Often, this is exactly why segmented ground planes (good in theory but VERY difficult in practice) fail. Digital should be seperate from analog, but IC's often contain both digital and analog. What ground do you connect too?
Anyway, take a look at increasing the number of components, to help alleviate board real-estate problems, and keep your ground plane solid! If your ground starts bouncing or sits at a higher potential (.25, .3, .35V, etc.) you are robbing the voltage from your circuit, and asking for trouble. If your IC is designed to run at 5V, would you want to supply it at 4.75V?
Good luck and keep us posted on your progress! (Great project!!!)
RE: GND plane vs. ESD protection choice
Chancy, how many of these are you planning to build? If it is a 100 or more, I can give you a source for 4 layers boards, that will cost about the same, or less, than 2 layers boards built in the U.S. That way you can have a solid ground plane, except for vias, under all your parts.
RE: GND plane vs. ESD protection choice
Thanks for the quick information. See below for a slightly older version of the layout. The connector and analog section are still the same. Look to the left side of the board.
http://www.avrfreaks.net/phorum/download.php?f=3&file=MegaLogger-pcb-V5b.pdf
The thread is at
http://www.avrfreaks.net/phorum/read.php?f=3&i=23140&t=23140#23140
Note the resistor arrays just inside of the connector, they feed into the dg333a muxes. The pacdn017 ESD array chip would go right under these on the bottom layer. The traces would go directly to the input pins on the connector.
There are a couple of bottom layer traces near there, but not much. When I do the copper pour, it fills in nicely. With that chip in place though, that whole section gets chopped up.
The analog and digital GND planes split right under the Mega128 cpu. The cpu is well covered by GND plane except where the decoupling caps are.
CalMicro also makes those arrays in a couple other sizes. The pacdn-016 is a 6 channel array, and they also have a 2 channel one. They will fit there as well, but it doesn't really help the chopping up of that bottom layer much. The single pacdn-17 is way easier ...
Dean.
RE: GND plane vs. ESD protection choice
Cool ! Thanks for the offer. I really have no idea how many of these will get built.
It was originally a project for myself and a few friends. I've had lots of request for it though, and can easily see a good 20-30. How much would that count be for the 4-layer ?
Dean.
RE: GND plane vs. ESD protection choice
1) Completely breadboard up your circuit and verify full functionality (esp. in vehicle). Nothing worse than finding a stupid logic error after you have spent several hundred (or possibly thousand) dollars. Might be a pain in the butt, but it will only help you! You can use the breadboarded version to develop your software, algorithms, timing verification, power assumptions, spike survival, anticipated waveform verification, etc.. Also, with a breadboarded version, you are not restricted by the number of components or size. Make it big and clunky, but put everything in it, even the kitchen sink! Put in headers to measure hard to get to signals, power, clocks, etc.. Once again, lots of work that can save you tons of time, money, and frustration after you get your PCB's.
2) Go 4 layers!!! Why kill yourself trying to fit it into 2 layers, when for a little bit more, you can have a solid power and ground plane? Especially if you have a fully functional breadboarded solution, then you can easily justify the couple of extra bucks for the 4 layer. Don't get fancy with trace size, min. 8 mil for digital signals, and min. 15 for power (obviously the bigger the better). Don't get crazy with vias either! Add multiple vias on power or high energy traces (via are inductive & resistive and putting them in parrallel decreases the inductance/resistance). Also, opt for the 100% electrical test. Nothing is more annoying that troubleshooting a "bad circuit" and finding out there is a short / open in the PCB.
Congratulations, it sounds like you are well on your way to completing a pretty interesting project!
RE: GND plane vs. ESD protection choice
In response to the question itsself I say the esd protection is more important.
For noise cancelation it is ok to cut up the ground plane as long as it is done right. The key is to have the ground plane look like a net with holes and lots of interlocking as opposed to fingers that just radiate away from the plane. That said it is still nicer to keep the ground plane as solid as possible.
I am assuming that you will mount this in an enclosure that will also help with noise cancelation.
BTW Nice Design, I can't wait to hear the results
RE: GND plane vs. ESD protection choice
I'm a breadboard manic. There are always several on the desk here, with various "ooh, let me try this" things on them. Unfortunately, this particular project is using quite a bit more SMD devices than I normally (if ever) play with. So breadboarding it is a little tough.
I am using the Atmel STK500/501 kits, and interfacing with all the thru-hole stuff now. That's fine and dandy, doing one bit at a time. The analog inputs I'll do with a few generic opamps (lm386 or something) and discretes. Use a 4016 or something as a switch instead of the DG333a. Proof of concept type deal.
So for some stuff, the pcb will be the breadboard :) The more eyes that spot glitches/gotchas before that happens, the better.
As for the GND plane, the ESD array chip will be way over on the left, right next to the 44pin connector. So it's really only over there just at signal entry that the plane will be broken to shreds. The rest of it should be OK. I think I'll keep it in.
It would be great to go with a 4layer board. But this is a project, not (yet anyway) a product :( So cost is definitely an issue. It was originally for myself and a couple of others. Though there has been enough interest to indicate it may later be worth doing a run of boards and making up kits, or perhaps building them myself. We'll see how it goes.
For 2layer boards, Olimex will do $26/ea, 4pcb will do $33/ea, and e-teknet is $25/ea. 4layer is basically double all that. I'm already at around $180 in parts alone, not including pcb ...
Oh, the enclosure is a Hammond 1455k1601 extruded alum ...
http://www.hammondmfg.com/1455.htm
Dean.
RE: GND plane vs. ESD protection choice
An ESD cap, will shunt the energy to ground, and only raise the ground voltage. Given the choice of exceeding the voltage ratings on a component, and not meeting the ratings, I would much rather save my components (and money), and cause the component to potentially stop operations due to insufficient power.
Anyway, I would highly recommend putting in the caps instead of the diodes. I design enginer controllers for one of the big 3 automakers, and am familiar with what ESD protection is included on engine controllers (VERY HARSH ENVIORNMENT). Plus, these caps should be cheaper than the diode array.
Did you get the SMD->Thru-pin sockets for all of your components? Some of them might be difficult to find, but let us know where you get stuck. I know for a fact that there are sockets that accept BGAs, PGAs, Gullwing, J-lead, etc..
Finally, why the aluminum case? Isn't it kinda expensive, when a sturdy plastic one will sufice? Are you thermally tying the PCB to the case for heat sinking?
RE: GND plane vs. ESD protection choice
I figured that given that these (the CalMicro arrays) are touted as ESD protection, the switchon time would be very quick. It's not noted in the datasheet though. Based on what you say, I think the caps are the way to go then, particularly since I have to make a choice :)
Can't fit both on the pcb - not enough room. So it's either the diode array or caps. Digikey sells a nice Panasonic capacitor array ...
http://www.digikey.com/scripts/us/dksus.dll?Detail?Ref=63630&Row=240537
They're 220pF, and two of those 6.4x3.1mm chips would fit nicely. Would 220pF be enough here, or do we have to go with individual caps ?
I have a couple of SMD prototyping mini-boards, but not yet for everything. Initial breadboard tests will be with thru-hole equivalents, just to validate things. Then I'll use the real things.
I like the Hammond enclosure :) Also, the extruded design with the mounting rails and end caps make it easy to handle the connectors etc. on each end of the board. I had originally started with a typical plastic project box, but getting the board down in there with the connectors protruding was problematical.
Dean.
RE: GND plane vs. ESD protection choice
The thing about ESD is that the results of an ESD shock are so unpredictable. You can shock the save device 10 times and not see any immediate circuit degredation, and shock the "same circuit" once and see catastophic failure. But here is the kicker, the worst case scenario is that there is a ESD hit, and there is no apparent failures, just degredation. This means that your circuit will fail at some later time for no apparent reason. This can cause huge amounts of effort in troublshooting the failure because the event that started the failure occured some time earlier.
Anyway, try looking at the individual caps. If those won't work in your layout, stick with the cap array, and locate it as close to the connector as possible. Finally, be meticulous in your routing of signals. Keep traces as far apart as possible, and do ground fills everywhere else. (He is working low enough frequencies that the change is track impedances due to change in surrounding ground islands will not really affect him.)
RE: GND plane vs. ESD protection choice
You can see a jpg of the analog input section, sans the GND plane at :
http://photos.yahoo.com/fnatmed
Just dig down into the My Photos section, and choose FullSize. Red is top layer, blue is bottom layer. The really thin lines are nets still to be completed. You'll see a bunch of them leading up off the top of the board. Up there are the footprints of the ESD array and two of the capacitor arrays.
The ESD chip would go right under the four 180k resistor packs, or the two cap-arrays would go there. Or a whole sea of 1206 size 0.1uF caps ...
Oh, what size caps ? Any particular type ? Thanks for the tips/help melone - I really appreciate it.
Dean.
RE: GND plane vs. ESD protection choice
About the help, no problem! This is exactly why this forumn is so useful. You have put in the effort, need help, and are not afraid to ask questions. We need more engineers with that type of work ethic!
RE: GND plane vs. ESD protection choice
Dang, an array would be much easier. Panasonic makes a 50V 1206-size array of 4 caps. Although rated at 50V, the dielectric will withstand 300% of rated voltage for 1-5 seconds. It actually says :
Class 1: rated voltage x 300%
Class 2: rated voltage x 250%
Would these do ?
http://rocky.digikey.com/WebLib/Panasonic/Web%20data/ECJ%20Array%20Type%20Series.pdf
Dean.
RE: GND plane vs. ESD protection choice
RE: GND plane vs. ESD protection choice
Dean.
RE: GND plane vs. ESD protection choice
RE: GND plane vs. ESD protection choice
Unfortuneately all of that won't help with the ESD that will no doubt come up your signal lines at times.
Myself I have always prefered diodes to caps but the apps I was dealing with were more geared twards having something left to repair after a catastrofic event, So I would say go with melone's concept it seams to be more appropriate for this application.
(I don't care if the design has protection diodes, it was struck by lightning , I can't fix it)
If you can't tell my experiance is in the service deparment.
RE: GND plane vs. ESD protection choice
Yup - it's version 1 of that enclosure with the alum. endcaps.
http://www.hammondmfg.com/1455.htm
Should be able to keep openings in those caps to a minimum.
Left
- DB25 size for the 44pin - typical metal shield
- Small round for locking Kycon power connector
Right
- USB device socket - typical metal shield
- slot for MMC card
- 2.5mm stereo socket for serial connection
For the caps, I think I'll go with slightly lower values, say 100pF. Want to keep the capacitance loading to a minimum.
*Next* version, with all the enhancements, will be on the 6x4 board, and will have room for everything :)
Dean.
RE: GND plane vs. ESD protection choice
RE: GND plane vs. ESD protection choice
RE: GND plane vs. ESD protection choice
If there's any learning to do, or any "Wouldn't it be cool if we could ... " it seems to grow a life of its own, extruding pseudopods of creeping featurism.
I will not, repeat, NOT, consider adding GPS mapping and auto-calibration for inputs until at least the Mk. II.
Dean.
RE: GND plane vs. ESD protection choice
http://www.digikey.com/scripts/us/dksus.dll?Detail?Ref=32989&Row=244318
Although either the 4-cap arrays with 50V ratings (again, 300% spike handling) or individual 100V or 250V 1206 caps would be better, I have to keep in mind that at the moment, this thing is to be built by hand.
Those 4-cap arrays cram 8 connectors along the sides of a 1206-sized piece (3.1mm x 1.6mm). That's just going to be too dang fiddley to try to solder. The 8-cap arrays is a bussed design, 8 connections with 2 end-GND connections, in a larger 5.1mm x 3.6mm package. Not much better, but here anything is better :)
Version II, if it ever gets designed/built, may be a production run. In which case I'll go with the tiniest bestest devices I can find. Pick-and-Place is a wonderful thing, but not when it's my fingers and eyes doing it ...
Dean.
RE: GND plane vs. ESD protection choice
RE: GND plane vs. ESD protection choice
When I first started in analog circuit design, when I was building my first prototype an older engineer asked what I would be building it on. I pulled out a breadboard -- I planned to deadbug the SMT components onto the breadboard for testing. He started laughing. Breadboards were for digital engineers, I was told.
Ever since I've gotten rid of the breadboard and now do all my prototyping dead bug on bare copper. This provides for a nice solid ground plane. It makes for some really nice more realistic low-noise low-distortion designs which don't fall apart at high frequency (a great deal of the work I do is in high frequency filters). It's easy to place all of your bypass caps everywhere you'd want them with as tiny leads as possible, and it's very easy to layout your circuit so that each component is as close (or as far) to each other as possible. Plus, your prototypes are easy to save and store for further use and reference. Sure, this requires you to brush up on your soldering skills, but under a microscope anyone can be a master solderer.
I've also had colleagues build similar prototypes dead-bug right on the surface of the PCB of an existing product being modified. This also works really well (a lot better than dragging wires out to some noisy breadboard somewhere).
Just a thought or two.
RE: GND plane vs. ESD protection choice
Thanks for the tips. I was planning on making a few small pcb's for testing. I did pspice up the analog section, and it appears to be doing exactly what was expected.
I used SwitcherCAD III from Linear Devices :
http://www.linear.com/software
These are the three variations that the circuit will provide - you can just paste these into single files and simulate them in SwitcherCAD. Plot V(inp), V(out) and I(R5).
Dean.
==========================
0-5V input maps to 0-5V output
Version 3
SHEET 1 892 692
WIRE 452 288 472 288
WIRE 436 292 412 292
WIRE 412 316 412 292
WIRE 412 292 392 292
WIRE 412 360 412 348
WIRE 444 296 444 348
WIRE 444 348 412 348
WIRE 412 348 412 336
WIRE 444 280 444 232
WIRE 472 288 472 252
WIRE 472 288 496 288
WIRE 472 252 436 252
WIRE 416 252 404 252
WIRE 424 212 288 212
WIRE 244 212 244 252
WIRE 244 348 280 348
WIRE 288 212 244 212
WIRE 436 284 404 284
WIRE 404 284 404 252
WIRE 404 252 348 252
WIRE 288 232 444 232
WIRE 444 232 444 212
WIRE 280 312 280 348
WIRE 280 348 312 348
WIRE 372 292 312 292
WIRE 312 292 280 292
WIRE 328 252 244 252
WIRE 244 252 244 348
WIRE 312 312 312 292
WIRE 312 328 312 348
WIRE 312 348 412 348
WIRE 544 288 544 348
WIRE 544 348 444 348
WIRE 532 288 544 288
WIRE 496 288 512 288
FLAG 412 360 GND
FLAG 496 288 OUT
FLAG 312 292 INP
SYMBOL voltage 448 212 R90
WINDOW 0 -8 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMATTR SpiceLine Rser=5
SYMBOL voltage 288 236 R180
WINDOW 0 6 26 Left 0
WINDOW 3 6 4 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMATTR SpiceLine Rser=5
SYMBOL Opamps\LT1367 444 272 R0
WINDOW 0 4 8 Left 0
WINDOW 3 4 24 Left 0
SYMATTR InstName U1
SYMATTR Value LT1367
SYMATTR Value2 LT1367
SYMATTR SpiceModel LTC.lib
SYMBOL res 440 248 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R1
SYMATTR Value 180k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 396 288 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R3
SYMATTR Value 180k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 416 340 R180
WINDOW 0 9 19 Left 0
WINDOW 3 9 10 Left 0
SYMATTR InstName R4
SYMATTR Value 100k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 508 292 R270
WINDOW 0 8 14 Left 0
WINDOW 3 0 14 Right 0
SYMATTR InstName R5
SYMATTR Value 1k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL voltage 280 288 R0
WINDOW 0 6 4 Left 0
WINDOW 3 6 26 Left 0
WINDOW 39 0 0 Left 0
WINDOW 123 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 0
SYMBOL res 352 248 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R2
SYMATTR Value 100k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL cap 308 312 R0
WINDOW 0 6 2 Left 0
WINDOW 3 6 16 Left 0
SYMATTR InstName C1
SYMATTR Value 220pF
text 242 372 Left 0 !.dc V3 0 20 .1
text 244 160 Left 0 ;MegaLogger analog input section\nMaps 0-5V input to 0-5V output
==========================
0-14V input maps to 0-5V output
Version 3
SHEET 1 892 692
WIRE 436 292 412 292
WIRE 412 316 412 292
WIRE 412 292 396 292
WIRE 412 360 412 348
WIRE 444 296 444 348
WIRE 444 348 412 348
WIRE 412 348 412 336
WIRE 444 280 444 232
WIRE 472 288 472 252
WIRE 472 288 496 288
WIRE 472 252 432 252
WIRE 412 252 404 252
WIRE 424 212 288 212
WIRE 244 212 244 348
WIRE 244 348 268 348
WIRE 288 212 244 212
WIRE 436 284 404 284
WIRE 404 284 404 252
WIRE 288 232 444 232
WIRE 444 232 444 212
WIRE 268 348 300 348
WIRE 376 292 312 292
WIRE 312 292 300 292
WIRE 452 288 472 288
WIRE 300 348 412 348
WIRE 544 348 444 348
WIRE 544 288 544 348
WIRE 496 288 508 288
WIRE 268 312 268 348
WIRE 300 312 300 292
WIRE 300 292 268 292
WIRE 300 328 300 348
WIRE 528 288 544 288
FLAG 412 360 GND
FLAG 496 288 OUT
FLAG 312 292 INP
SYMBOL voltage 448 212 R90
WINDOW 0 -8 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMATTR SpiceLine Rser=5
SYMBOL voltage 288 236 R180
WINDOW 0 6 26 Left 0
WINDOW 3 6 4 Left 0
WINDOW 123 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMATTR SpiceLine Rser=5
SYMBOL Opamps\LT1367 444 272 R0
WINDOW 0 4 8 Left 0
WINDOW 3 4 24 Left 0
SYMATTR InstName U1
SYMATTR Value LT1367
SYMATTR Value2 LT1367
SYMATTR SpiceModel LTC.lib
SYMBOL res 436 248 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R1
SYMATTR Value 180k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 400 288 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R3
SYMATTR Value 180k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 416 340 R180
WINDOW 0 9 19 Left 0
WINDOW 3 9 10 Left 0
SYMATTR InstName R4
SYMATTR Value 100k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 504 292 R270
WINDOW 0 8 14 Left 0
WINDOW 3 0 14 Right 0
SYMATTR InstName R5
SYMATTR Value 1k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL voltage 268 288 R0
WINDOW 0 6 4 Left 0
WINDOW 3 6 26 Left 0
WINDOW 39 0 0 Left 0
WINDOW 123 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 0
SYMBOL cap 296 312 R0
WINDOW 0 6 2 Left 0
WINDOW 3 6 16 Left 0
SYMATTR InstName C1
SYMATTR Value 220pF
text 242 372 Left 0 !.dc V3 0 20 .1
text 244 162 Left 0 ;MegaLogger analog input section\nMaps 0-14V input to 0-5V output
==========================
9-14V input maps to 0-5V output
Version 3
SHEET 1 892 692
WIRE 452 288 472 288
WIRE 436 292 412 292
WIRE 412 316 412 292
WIRE 412 292 396 292
WIRE 412 360 412 348
WIRE 444 296 444 348
WIRE 444 348 412 348
WIRE 412 348 412 336
WIRE 444 280 444 232
WIRE 472 288 472 252
WIRE 472 288 496 288
WIRE 472 252 436 252
WIRE 416 252 404 252
WIRE 424 212 288 212
WIRE 244 212 244 348
WIRE 244 348 280 348
WIRE 288 212 244 212
WIRE 436 284 404 284
WIRE 404 284 404 252
WIRE 404 252 348 252
WIRE 528 288 548 288
WIRE 288 232 304 232
WIRE 444 232 444 212
WIRE 280 312 280 348
WIRE 280 348 308 348
WIRE 376 292 312 292
WIRE 312 292 308 292
WIRE 328 252 304 252
WIRE 304 252 304 232
WIRE 304 232 444 232
WIRE 308 312 308 292
WIRE 308 292 280 292
WIRE 308 328 308 348
WIRE 308 348 412 348
WIRE 548 288 548 348
WIRE 548 348 444 348
WIRE 496 288 508 288
FLAG 412 360 GND
FLAG 496 288 OUT
FLAG 312 292 INP
SYMBOL voltage 448 212 R90
WINDOW 0 -8 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMATTR SpiceLine Rser=5
SYMBOL voltage 288 236 R180
WINDOW 0 6 26 Left 0
WINDOW 3 6 4 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMATTR SpiceLine Rser=5
SYMBOL Opamps\LT1367 444 272 R0
WINDOW 0 4 8 Left 0
WINDOW 3 4 24 Left 0
SYMATTR InstName U1
SYMATTR Value LT1367
SYMATTR Value2 LT1367
SYMATTR SpiceModel LTC.lib
SYMBOL res 440 248 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R1
SYMATTR Value 180k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 400 288 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R3
SYMATTR Value 180k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 416 340 R180
WINDOW 0 9 19 Left 0
WINDOW 3 9 10 Left 0
SYMATTR InstName R4
SYMATTR Value 100k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL res 504 292 R270
WINDOW 0 8 14 Left 0
WINDOW 3 0 14 Right 0
SYMATTR InstName R5
SYMATTR Value 1k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL voltage 280 288 R0
WINDOW 0 6 4 Left 0
WINDOW 3 6 26 Left 0
WINDOW 39 0 0 Left 0
WINDOW 123 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 0
SYMBOL res 352 248 R90
WINDOW 0 0 14 Right 0
WINDOW 3 8 14 Left 0
SYMATTR InstName R2
SYMATTR Value 100k
SYMATTR SpiceLine tol=5 pwr=0.25
SYMBOL cap 304 312 R0
WINDOW 0 6 2 Left 0
WINDOW 3 6 16 Left 0
SYMATTR InstName C1
SYMATTR Value 220pF
text 242 372 Left 0 !.dc V3 0 20 .1
text 244 168 Left 0 ;MegaLogger analog input section\nMaps 9-14V input to 0-5V output
==========================