How to improve SDRAM clock signal?
How to improve SDRAM clock signal?
(OP)
Hi,
The SCLK of the SDR SDRAM on my layout looks like a sine wave! Its rise and fall times are so slow that there is not enough time for the required high or low timing.
There is only one SDRAM chip on the design. The clock line length is about 3 inches. I already use maximum drive strength but it's still not enough. The clock runs at 133MHz.
What else can I do?
Regards,
James
The SCLK of the SDR SDRAM on my layout looks like a sine wave! Its rise and fall times are so slow that there is not enough time for the required high or low timing.
There is only one SDRAM chip on the design. The clock line length is about 3 inches. I already use maximum drive strength but it's still not enough. The clock runs at 133MHz.
What else can I do?
Regards,
James





RE: How to improve SDRAM clock signal?
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RE: How to improve SDRAM clock signal?
Dan - Owner

http://www.Hi-TecDesigns.com
RE: How to improve SDRAM clock signal?
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RE: How to improve SDRAM clock signal?
James
RE: How to improve SDRAM clock signal?
750MHz is just barely 5x the fundamental. Even a perfect square wave is going to be rounded off with that frequency response. Don't forget that stated bandwidths are usually 3dB, which means that you're only getting 50% response at that frequency, so your 5th harmonic is reduced by 50%.
Again, is your circuit working at all?
TTFN
FAQ731-376: Eng-Tips.com Forum Policies
Chinese prisoner wins Nobel Peace Prize
RE: How to improve SDRAM clock signal?
RE: How to improve SDRAM clock signal?
Dan - Owner

http://www.Hi-TecDesigns.com
RE: How to improve SDRAM clock signal?
Keith Cress
kcress - http://www.flaminsystems.com