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Drive a piezo buzzer (cep_2242) from a 3.3V FPGA output?
2

Drive a piezo buzzer (cep_2242) from a 3.3V FPGA output?

Drive a piezo buzzer (cep_2242) from a 3.3V FPGA output?

(OP)
Hello,

Goal: Drive a cep_2242 piezo buzzer from a 3.3V FPGA output. Driving direct from FPGA does not generate the required sound volume, not surprising considering the buzzer operating voltage is 3-16 Vdc (7mA max at 12V).

I would like to use an integrated load switch, so I can provide 12V to the buzzer and on/off with the FPGA output.

My question is:  Can someone recommend a load switch which will work with the 7mA max current drawn by the buzzer?  

Maybe similiar to the FDC6324L (Vin 3-20V range / on 1.5-8V) but with a much lower load current minimum when on.

Thank you,
Chris  
 
 

RE: Drive a piezo buzzer (cep_2242) from a 3.3V FPGA output?

How about an op-amp amplifier? Many op amps can handle 7mA.

RE: Drive a piezo buzzer (cep_2242) from a 3.3V FPGA output?

Do schools no longer teach simple switching using a single transistor or FET?  At 7mA, even a lowly 2N2222 will work...

Dan - Owner
http://www.Hi-TecDesigns.com

RE: Drive a piezo buzzer (cep_2242) from a 3.3V FPGA output?

"2N2222"

Amen.

Or perhaps a 2N2907 if you wish to 'reverse' the circuit.


Good thing that Dan got here before someone recommended a single board computer. winky smile


 

RE: Drive a piezo buzzer (cep_2242) from a 3.3V FPGA output?

Yeah, do what Dan suggested. Take a 10k resistor from your FPGA to the base of a 2N2222. Your buzzer goes from the collector to your 12V. I've played with those cheap buzzers from radio shack years ago and the DC offset didn't affect the operation. The 10k is more than you need, you don't need to saturate the transistor.

RE: Drive a piezo buzzer (cep_2242) from a 3.3V FPGA output?

Have you tried bridging it?  That will double the voltage. We tweeked the frequency of each unit so it operated at resonance.  That will increase the sound level a lot.

RE: Drive a piezo buzzer (cep_2242) from a 3.3V FPGA output?

(OP)
Thanks for all the input, I included a circuit diagram in case anyone else finds themselves down the same path smile

I added a 10K pull-down from the base to cover FPGA reset, where the IO pin floats.  As suggested, I used a 10K resistor between the 3.3V FPGA output and the 2N3904 NPN base to set collector current.  DRIVEPOWER (see diagram) varies from 5V-12V.

If anything doesn't look right, please advise.

I was a little surprised the buzzer (cep_2242, max 7mA at 12V) does not require a current limiting resistor (as an LED does). I tested it directly with a 12V supply seemingly without issue.

Happy Thanksgiving,
Chris

RE: Drive a piezo buzzer (cep_2242) from a 3.3V FPGA output?

I'd make the pull-down 100k (assuming the pin's leakage current is okay with that).

To be honest, I'd probably put the current-set resistor in the emitter, not the base... otherwise you're counting on the beta of the transistor to be constant from unit to unit (and to be fair, they generally are pretty good, even with the cheapest of transistors).

Dan - Owner
http://www.Hi-TecDesigns.com

RE: Drive a piezo buzzer (cep_2242) from a 3.3V FPGA output?

(OP)
> I'd make the pull-down 100k (assuming the pin's leakage
> current is okay with that).

Could you be more descriptive? Why would you make the
pull-down 100k instead of 10K?

Thanks!

RE: Drive a piezo buzzer (cep_2242) from a 3.3V FPGA output?

With the pull-down at 10k, a high on the FPGA pin shows up as half-voltage at the base of the transistor... a 3.3V FPGA will drive the transistor base to 1.65V (actually, a bit less considering the amount of current into the base of the transistor).  Not a very good situation.

From a design standpoint, it's also wasteful of power, losing 50% of your pin current through a pull-down.  Not a big deal here, but add enough drivers like that and the power adds up quickly.

Just make sure whatever you set it at can handle the leakage current of the pin without dragging the base high enough to turn it on.

Dan - Owner
http://www.Hi-TecDesigns.com

RE: Drive a piezo buzzer (cep_2242) from a 3.3V FPGA output?

(OP)
> With the pull-down at 10k, a high on the FPGA pin shows
> up as half-voltage at the base of the transistor... a
> 3.3V FPGA will drive the transistor base to 1.65V
> (actually, a bit less considering the amount of current
> into the base of the transistor).

Good point, the MMBT3904 datasheet lists the Base-Emitter
Saturation Voltage at 0.95V max in the "ON characteristics"
section.  So it seems we are OK with the half divider, as
the voltage exceeds the 0.95V required to turn ON the
amplifier.

Any reason to believe this is *not* enough margin for the
amplifier to turn on?

Thanks.

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