CMOS current limiting and paralleling output
CMOS current limiting and paralleling output
(OP)
Hello,
I have been involved in modifications on the existing device using CMOS ICs with which I do not have practical experience and for this reason I would like to ask few questions.
In new circuit I would have to connect the output of LM339 with CD4013B flip flop. I have found article recommending series resistor between comparator and CMOS:ht tp://www.e celab.com/ interfacin g-opamp-tt l-cmos.htm .My case is Fig.1 with 12V supply. My question is about the resistor sizing why exactly the 10K value is selected? After some research I have found the upper limit of resistor value is given by a time constant of Rlim and gate&PCB tracks capacitance , that in the case of 15 VDD supply CMOS the rise time of the input signal should not exceed 4-5us to avoid output oscillations.
I assume the lower value is given by the maximum allowed input current to the gate when internal clamping diodes are activated by ESD or transient overvoltage. Here I found in datasheet http://www.fairchildsemi.com/ds/CD/CD4013BC.pdf only the IIN = 1uA which seems to me as the maximum current in normal operation defining input resistance quality not the maximum current allowed for clamped input. Shall I search maximum allowed gate current in some general logic family datasheet? I assume after finding this info the minimum resistor value shall be Umax expected/ I max.
My second question is about paralelling 2 outputs of CMOS IC. I think I have seen this in circuits when the IC was connected to power MOSFET in order to achieve faster switching. Are there any precautions before paralleling outputs? Concretelly I would like to drive 17mA signal relay coil with two parallel CD4049B outputs sinking coil via outputs to ground where maximum 12mA per output is recommended for continous operation.
I have been involved in modifications on the existing device using CMOS ICs with which I do not have practical experience and for this reason I would like to ask few questions.
In new circuit I would have to connect the output of LM339 with CD4013B flip flop. I have found article recommending series resistor between comparator and CMOS:ht
I assume the lower value is given by the maximum allowed input current to the gate when internal clamping diodes are activated by ESD or transient overvoltage. Here I found in datasheet http://www.fairchildsemi.com/ds/CD/CD4013BC.pdf only the IIN = 1uA which seems to me as the maximum current in normal operation defining input resistance quality not the maximum current allowed for clamped input. Shall I search maximum allowed gate current in some general logic family datasheet? I assume after finding this info the minimum resistor value shall be Umax expected/ I max.
My second question is about paralelling 2 outputs of CMOS IC. I think I have seen this in circuits when the IC was connected to power MOSFET in order to achieve faster switching. Are there any precautions before paralleling outputs? Concretelly I would like to drive 17mA signal relay coil with two parallel CD4049B outputs sinking coil via outputs to ground where maximum 12mA per output is recommended for continous operation.





RE: CMOS current limiting and paralleling output
the 10k resistor is not really needed if your LM339 is powered from the same supply as your CD4013. If they have different supplies that may both be 12 V, then it's needed to prevent the LM339 under power to send 12 V to the CD4013 that might not have power (think also power sequencing).
The 10k is probably selected to limit the current through the CD4013 protection diodes to a safe level.
Second question: paralleling can be done without any problems.
Benta.
RE: CMOS current limiting and paralleling output
RE: CMOS current limiting and paralleling output
Thanks for the paralleling confirmation. It seems it is pretty much the same as in the case of the discreete transistors. Even less painful for the transistors on chip because they are better matched with the switching characteristics. I do remember some application note when for paralleling discreete Mosfets some low pass filter with inductance on gates was recommended to better match the switching controlled with the same signal.
RE: CMOS current limiting and paralleling output
RE: CMOS current limiting and paralleling output
For the switching characteristic I have found only the timing characteristic but the transient Cgate charge current should not be an issue ( if I look in situation when one IC output is supplying the second IC input both CMOS ), is that correct?
I was assuming the current limiting resistor is necessary only for the situation where the internal diodes are clamped in the situation the longer transient overvoltage is expected that the one used in ESD protection testing using human body model. So this is why I am a bit confussed now.
RE: CMOS current limiting and paralleling output
With two capacitors collected in parallel like this you can get some oscillation as they pass charge back and forth; as thsi varies Vgs slightly you can see it on the drain/source channel. A bit of filtering between the gates reduces this effect. This is typically only an issue in high frequency circuits (transmission line reflections).
I consider this similar to adding a resistor in series with the base on a BJT so you don't get ringing caused by the inductance on the emitter lead.
John D
RE: CMOS current limiting and paralleling output
ON Semiconductor does, if you check out the MC14013, maximum input (and output) current is specified as +/- 10 mA.
Benta.
RE: CMOS current limiting and paralleling output
Hope this helps
RE: CMOS current limiting and paralleling output
There will be a potential transient input current draw if the CLK input is potty, causing the internal feedback path to be transiently connected to the data input.
Fairchild's datasheet DOES specify maximum output current of 8.8 mA at Vout=1.5V.
Likewise, the ON datasheet shows max input current of 1 uA
TTFN
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RE: CMOS current limiting and paralleling output
Benta, thanks this current value now makes a sense for me with 10k resistor.
The LM339 is OC indeed, I have connected the pull-up to its output right after placing the comparator.
Now I have finally some idea about current limiting resistor size considerations.
RE: CMOS current limiting and paralleling output
Yes I was talking about ESD diodes ( or maybe for some ICs the reverse polarity protection ).
Normal operation is out of question there is no need to do any limiting. My question was related to sizing consideration of series limiting resistor which is recommended when the input of the MOS is connected to edge connector at http://ww
RE: CMOS current limiting and paralleling output
Since the 14000 series CMOS are pretty much slugs as propagation delays go, you can pick higher resistances to provide more ESD protection.
TTFN
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RE: CMOS current limiting and paralleling output
But what is the mening of 10K capacitor between comparator and CMOS. My idea is now the ESD diodes and the resistor creates a lowest possible resistance for a very short duration ESD which current is decreasing in time (as for capacitor discharge ). The eventual transient voltage exceeding VDD+Vd when comparators output going 0V to +Vs or Vss-Vd when going from +Vs to 0V would create practically a short via ESD diodes with a current source represented by comparators output which is not limited compared with ESD capacitor discharge nature and should damage the ESD diodes.
Is this a reason for use this resistor? If yes should it be ommited if the eventual transient voltage on comparator would not exceed levels activating ESD diodes?
RE: CMOS current limiting and paralleling output
> minimization of ringing and other high frequency noises not relevant to the actual signal
> isolation of failed components, so if the driven gate gets fried and shorted out, it does not cause an output failure in the upstream device.
TTFN
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RE: CMOS current limiting and paralleling output
So if I understand it well in this case the priority is limiting and additionally the resistor together with Cgs and PCB track capacitance forms a parasitic but in this case usefull low pass filter.
Thanks again for answer now the resistor sizing is much much more clear for me in different connections.
RE: CMOS current limiting and paralleling output
Let me add to your understanding by providing you with a real world example. I designed a PCB that had a CPLD on it that had a nominal input range of +3.3Vdc with some margin (I forget how much). I made a design fubar where instead of +3.3V, I accidentally applied +7vdc to the input when it was high.
Fortunately, I followed "good design practice" and put a current limiting resistor on the CMOS input to the CPLD. The clamping diode in the CPLD kept the voltage applied to the internal circuitry within limits. The resistor was such that it limited the current through the diode and kept it from being destroyed. The net result was that even though there was a serious flaw in the design, I was able to still use it for prototyping purposes and avoided a costly board re-spin. Without the current limiting diode, the CPLD would have gotten really hot, really fast and quickly failed.
RE: CMOS current limiting and paralleling output
So if I get it from information above correctly the resistor sizing consideration for interfacing should be following:
1.) Determine the minimum value according the current carrying capacity of the output of the upstream device connected to CMOS for the worst case direct short of the CMOS to ground.
2.) Theoretically then I should calculate the time constant of limiting resistor and Cgs and PCB track and determine the resistor value which will provide me desired maximum rise time (transfer delay ) but at the same time not exceeding the maximum rise time allowed for the given IC type. Practically maybe instead of calculation it would be better ( for me ) to increase repetitively the value of resistor and measure the dynamic parameters.
The with theoretical or practical approach get as high limiting resistor value as possible fulfilling the required dynamic parameter.
For the ESD immunity increasing via introducing serial resistor in connector leading out of board I will rather consult some book because I have a feeling it is not so easy...