SMPS control loop compensation
SMPS control loop compensation
(OP)
Hello,
Apologise if this is more investigative though i feel sure it will be of interest to many.
Recently i attended a seminar in Reading , UK from Linear Technlogy about their circuit simulator which is used in SMPS design.
~90 SMPS engineers were in attendance.
At one point, the speaker stopped and posed a question to the audience. He put up a non isolated buck schematic. He pointed to the load side of the inductor, then to the input of the error amplifier in the PWM controller (it was either there or the output of the PWM comparator, i forget).
-He then asked what was the phase difference between those two points....was it 0 degrees, -90 degrees or +90 degrees ?
Only one person gave the correct answer...which was zero degrees...one person in 90....and i believe he was a stooge in the audience because he appeared to know the Linear people.
I think this is an indication that many (at least UK) SMPS engineers struggle with the control loop aspects of switch mode design.
I also struggle with this and recently have read over 100 app notes, documents and various book chapters........however, i am now looking for a document which shows waveform shots of SMPS's which have ....
1. Correctly compensated control loops
2. Incorrectly compensated control loops.
...and give the reason for the incorrectness.
There are basically three or 4 error amp circuits used in SMPS compensation...using few R's and C's......i reckon good transient response can be achieved emperically.
For example, if the circuit oscillates after a load transient then it's obvious that the error amp feedback resistor value is too high - and/or the feedback capacitor value is too low.
I reckon that if the phase margin is too low...then there is too much oscillation after a load transient.
-If the gain margin is too low...then the overshoot is too much when a load transient occurs.
I would be very grateful if readers knew of any documents showing the actual scope shots and waveforms that would be seen in poorly compensated SMPS's?.....and giving the reason for the poor performance?
Apologise if this is more investigative though i feel sure it will be of interest to many.
Recently i attended a seminar in Reading , UK from Linear Technlogy about their circuit simulator which is used in SMPS design.
~90 SMPS engineers were in attendance.
At one point, the speaker stopped and posed a question to the audience. He put up a non isolated buck schematic. He pointed to the load side of the inductor, then to the input of the error amplifier in the PWM controller (it was either there or the output of the PWM comparator, i forget).
-He then asked what was the phase difference between those two points....was it 0 degrees, -90 degrees or +90 degrees ?
Only one person gave the correct answer...which was zero degrees...one person in 90....and i believe he was a stooge in the audience because he appeared to know the Linear people.
I think this is an indication that many (at least UK) SMPS engineers struggle with the control loop aspects of switch mode design.
I also struggle with this and recently have read over 100 app notes, documents and various book chapters........however, i am now looking for a document which shows waveform shots of SMPS's which have ....
1. Correctly compensated control loops
2. Incorrectly compensated control loops.
...and give the reason for the incorrectness.
There are basically three or 4 error amp circuits used in SMPS compensation...using few R's and C's......i reckon good transient response can be achieved emperically.
For example, if the circuit oscillates after a load transient then it's obvious that the error amp feedback resistor value is too high - and/or the feedback capacitor value is too low.
I reckon that if the phase margin is too low...then there is too much oscillation after a load transient.
-If the gain margin is too low...then the overshoot is too much when a load transient occurs.
I would be very grateful if readers knew of any documents showing the actual scope shots and waveforms that would be seen in poorly compensated SMPS's?.....and giving the reason for the poor performance?





RE: SMPS control loop compensation
Following your own examples, any abrupt load transient in the time domain means a wideband noise rushing into your amplifier. Too much resistance means more gain, so your feed back loop will oscillate with their own natural frequency.
If the control loop is too 'deaf' (showing poor gain at high frequencies), we may have overshoot. In off-line PS, sometimes this also produces line noise at the output of flybacks, because the control loop can't track the 100/120Hz line changes fast enough.
Oscillation often helps finding hidden parasitics in the circuit, helping on calculating more accurate filter parameters.
RE: SMPS control loop compensation
RE: SMPS control loop compensation
I just designed a 35W flyback and calculated using C = i dt / dv (with Marty Brown's method) that i needed about 100uF of capacitance on the output.
However, with the cheap electrolytics that i am using, they have such low ripple current rating that i am ending up needing to put some 3mF on the output to handle the ripple current of ~2A.
This means that the output pole frequency = 1/2.pi.R.C is now very low and i will have to tailor the compensation components accordingly. I can only see that with this much capacitance on the output i am going to get a long lasting oscillation after any large load transient, no matter what compensation components i use.
I will have to set the zero gain crossover frequency very low and wondered if their is advice to be given on this matter?
RE: SMPS control loop compensation
RE: SMPS control loop compensation
If the original circuit which the instructor pointed to has only one resistor as the link between the load and the error amp, the phase shift is obviously zero. A red flag pops up in my mind though. The error amp input is a very convenient location (and a very common location) to place a lead-lag network made of one more R and a C. the zero is usually set to a value below the output filter resonance so that it adds phase before the 180deg negative shift of the filter.
Concerning the ESR of your filter caps, it adds a zero, not a pole as you wrote. You should use the resulting zero to your advantage to increase the bandwidth, not decrease it.
RE: SMPS control loop compensation
RE: SMPS control loop compensation
With SMPS, what occasionally bites me is noise due to sub-optimal pcb trace layout.
Claude
RE: SMPS control loop compensation
RE: SMPS control loop compensation
http://powerelectronics.com/mag/50107.pdf
.....seems to tell a different story about how to do isolated feedback with an opto and TL431.
...And figure 3 (2nd page) of the above article has a bias resistor into the cathode of TL431......Yet no such resistor appears in the books of Marty Brown (cookbook) or Ray Macks book (demystifying smps).
Most interesting of all is the LNK series offline PWM controllers from Power Integrations.....
http
....these do not require any feedback compensation components...and yet give excellent regulation...they use simple ON/OFF control.
...The LNK series are for just say ~10 Watts in offline use.....however, i am sure this power range could be extended much higher.....the only problem being that ON/OFF controllers operate in burst mode and the low frequencies inherent in the burst patterns can get through the EMC filter and cause conducted emissions problems....
-This leads to the realisation that one of the main concerns of feedback compensation is actually EMC....-and the poorer your transient response...generally the better your EMC is because your poor transient response is due to the fact that your pulse to pulse widths are changing too slowly and smoothly to give good regulation....however, this creates a power supply with an easier to filter EMC signature.
-However it makes me less keen to get a good transient response, as i don't fancy failing at the costly EMC test house.
RE: SMPS control loop compensation
Some folks feel (I'm not one of them) that pseudo random frequency modulation of a PWM carrier frequency is an EMI "Cheat." But if it is a natural fallout of the control scheme used, is this still a "Cheat" or simply Damned Good Design? A star for you marginal.