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buffer interface between tester and target board

buffer interface between tester and target board

buffer interface between tester and target board

(OP)
Hi, got myself a boundary testing device and mainboard and want to create a breadboarded interface between the two to protect the target from any issues that crop up from our tester, which has been faulty in the past.

Any tips on how I can design this with npn transitors?

RE: buffer interface between tester and target board

(OP)
been trying to pry that information out of corelis but they won't budge :(

RE: buffer interface between tester and target board

(OP)
there is a 33kohm resistor that goes to each of the TAP connections to bring current down, no other protection. That should be enough, but I would like another layer.

RE: buffer interface between tester and target board

Well, you should use integrated buffer chips, if nothing else, duplicate the I/O buffers on your board.  You're not going to be able to build meaningfully performing buffers out of discrete transistors, unless you're running an absurdly low clock rate system.

TTFN

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