oscillator bank
oscillator bank
(OP)
Hi all, I'm a software/DSP guy currently a bit over my head designing some hardware. I have a design in mind for my problem, but it's based on technology I would have used to do this twenty years ago. So I am writing in hopes of getting a "sanity check" on my solution.
Problem: build an 128-oscillator bank. Frequencies: 24000 Hz, 24093.75 Hz, 24187.5 Hz, ... 35906.25 Hz. Each oscillator must be on a different physical connection, for a capacitive sensor application. The spacing corresponds to a 1024-point FFT at 96kHz. Since they are all within one octave, the signals can be square waves (only the fundamental matters). Frequency accuracy needs to be 0.01% (+-4 Hz at 40kHz). Power needs I'm not too sure of yet, let's say a handful of mW at 5V for each oscillator.
This is a prototype that I will have to build. If it were a product, my solution would be: hire someone to design something, probably involving an ASIC...
Solution: The outputs are driven by TTL octal latches. A microprocessor (PIC) addresses the latches a byte at a time through some more TTL logic. The microcode updates a software counter for each oscillator and updates the latches when needed.
A vague solution, but hopefully precise enough to ask: is this at all the right technology to use? The correspondence of the frequencies to the bins of the FFT led me to think about solutions that would use this property to advantage. But it's hard to see how to do that given the need for separate outputs.
Problem: build an 128-oscillator bank. Frequencies: 24000 Hz, 24093.75 Hz, 24187.5 Hz, ... 35906.25 Hz. Each oscillator must be on a different physical connection, for a capacitive sensor application. The spacing corresponds to a 1024-point FFT at 96kHz. Since they are all within one octave, the signals can be square waves (only the fundamental matters). Frequency accuracy needs to be 0.01% (+-4 Hz at 40kHz). Power needs I'm not too sure of yet, let's say a handful of mW at 5V for each oscillator.
This is a prototype that I will have to build. If it were a product, my solution would be: hire someone to design something, probably involving an ASIC...
Solution: The outputs are driven by TTL octal latches. A microprocessor (PIC) addresses the latches a byte at a time through some more TTL logic. The microcode updates a software counter for each oscillator and updates the latches when needed.
A vague solution, but hopefully precise enough to ask: is this at all the right technology to use? The correspondence of the frequencies to the bins of the FFT led me to think about solutions that would use this property to advantage. But it's hard to see how to do that given the need for separate outputs.





RE: oscillator bank
Obviously, stand-by for more elegant suggestions.
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RE: oscillator bank
Thanks VE1BLL, this is a good idea. Since my frequencies don't have to be very accurate, I can probably fudge the LCM a lot too.
RE: oscillator bank
RE: oscillator bank
Be aware that the top end of the required address space will probably be set by your design parameters, and is unlikely to be a simple number like 2^N. In other words, assume at the outset that you'll need an arbitrary end point that may be a run-of-the-mill obscure number.
It used to common (well, relative to this very obscure topic) to look for opportunities to just store one-half, or even one-quarter, of the waveform and then combine counting backwards and inverting the output to complete the entire cycle. But these days memory is probably cheaper than counting backwards and certainly cheaper than inverting the output on command.
My gut just told me that you might have a clocking challenge as well. The tinyness of the time step (high F clock) required smells like it will be function of how accurately placed you need all the edges. This would be probably also be solved by breaking up the 128 into banks of a much smaller N (like 8 for example).
RE: oscillator bank
Dan - Owner

http://www.Hi-TecDesigns.com
RE: oscillator bank
Keith Cress
Flamin Systems, Inc.- http://www.flaminsystems.com
RE: oscillator bank
In other words, there will be a minimum processing loop heart-beat that isn't likely to be perfectly in phase with the theoretically-perfect schedule of transitions. Unless you can arrange for the processor clock to be a LCM of the schedule (and that might be pretty high if the channel count per processor is high).
It might require some clever system design and programming to keep the phase noise in check. Part of the solution would be to slide the waveforms in relative phase to eliminate transitions that are too close together to accomplish with a given processing speed, and too far apart to combine in the schedule without causing excess phase noise.
Another trick would be, if using two packages, to distribute the too-close transitions between the two packages.
Or check the phase noise requirement. Perhaps it's wide enough that it's not really an issue.
What's that old joke?
"Daddy, what is 'Time' ?"
"Son, time was invented so that everything doesn't happen at once."
RE: oscillator bank
You're not going to be able to get your transitions to be within a window like that if you're polling a timer and banging ports. You'd have a lot more jitter than 0.01%.
RE: oscillator bank
macgyvers2000 - Thanks! Any examples of what kind of processors you mean? A TTL solution is appealing if I can get away without buffering each output after the logic -- don't know if that would be possible with a microprocessor.
RE: oscillator bank
Since the phase doesn't matter, the accuracy is directly tied to the accuracy of the processor's crystal. Since you can order 50ppm crystals from Digi-Key for $2, that's taken care of nicely.
I take back my earlier statement... I might use external chips. In this case, some flip-flops would be useful. Have the PICs output a series of (93.75Hz * n) signals by setting up a timer to interrupt every (93.75Hz * 128) times and change the appropriate signal lines. Heterodyne the signals with a 40kHz wave using the flip-flops and you have a seriously large array of signals spaced at 93.75Hz intervals starting at 40kHz with 50ppm accuracy. Signals will be in-phase in groups of 8, but since that wasn't a requirement, who cares.
Dan - Owner

http://www.Hi-TecDesigns.com
RE: oscillator bank
24000 = 93.75 * 256
24093.75= 93.17 * 257
etc.
This will give you 100% coherency between the output frequencies and phases.
Regards,
Benta.
RE: oscillator bank
"by setting up a timer to interrupt every (93.75Hz * 128)"
I can't quite put my finger on it yet, but my gut tells me that the above isn't quite correct. I think that the multiplication function needs to be replaced with an LCM function. 12,000 Hz (93.75Hz*128) sounds much too easy.
Here's some LCMs just for laughs:
LCM (first 64, 24000 to 29906.25) = 2.6873E+255
LCM (first 77) = 6.0832E+302
LCM (first 78) = #NUM! (error)
The hetrodyning concept helps, but you still end up with three digit exponents.
LCM (93.75 to 5906.25, first 63) = 1.7139E+185
These will probably be the biggest numbers that you'll see all month. Except perhaps your post-Xmas credit card bill.
RE: oscillator bank
You'd first have ONE 93.75 Hz oscillator.
Then, for each frequency you have a phase/frequency detector, a VCO and a feedback counter.
This you could probably put into an FPGA 128 times. You'd need the VCOs to be external, but 128 counters and 128 phase detectors is a piece of cake. The simplest phase detector is just an EXOR gate.
Benta.
RE: oscillator bank
RE: oscillator bank
Neat concept. But it'll be a big box with all those VCOs.
But since ANY solution probably needs 128 BNC output jacks anyway, even a one-chip solution will probably end up in a the same size big box.
RE: oscillator bank
Now, what chip would you use for that?
IRstuff tipped me about the Parallax Propeller once. And I have used it a lot since that. It is fast, you can clock it at 100 MHz, which is good for a bit banger. It is a 32 bit chip. Which means that resolution or word length is seldom a problem. It has 32 I/O on each chip. So you don't need more than four chips for your 128 signals.
If it can do it? Fast enough? Yes, I guess so. And if one processor cannot handle it, there are eight of them on the chip. So each processor needs only handle four I/Os.
Power hungry? Yes, if around 50 mA is power hungry.
Expensive? Yes, if around 10 bucks is expensive.
Have a look at it - and smile.
Gunnar Englund
www.gke.org
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100 % recycled posting: Electrons, ideas, finger-tips have been used over and over again...
RE: oscillator bank
A hardware solution if yoy can relax the frequency accuracy a bit.
Start with a 12 bit counter running at 100 MHz (10 ns). With a comparator you short cycle the count to half the period you want. Then toggle another flip flop to get a square wave at the frequency you want.
So for example
2083 counts /2 = 24,004 Hz
2075 counts /2 = 24,096 Hz
.
.
.
1393 counts /2 = 35,893 Hz
1392 counts /2 = 35,919 Hz
Then for 128 13 bit counters you will need 16,000 plus flip flops. But in todays programmable logic devices, that's not a staggering number. You might have to use, say, 4 or 8 devices. A call to Altera, Actel or Lattice would confirm what you need.
These devices are pretty cheap and can be programmed onboard with a serial link from a PC. And the design software is free (and easy to use). And you really only need to design one counter, they are all the same except for the short cycle count number.
The frequency accuracy increases if the clock frequeny is increased but this increases the flip flop count. With multiple PLDs, one might be able to have slightly different clock frequencies (like 99, 100, 101, etc. MHz) to improve the likelyhood of finding a count that more closely matches the final frequency desired.
RE: oscillator bank
The timing limits at 40 kHz are 1000000/40004 = 27.9975 us and 1000000/39996 = 25.0025 us. That is an interval being equal to 5 nanoseconds. Actually half of that since the waveform has to be toggled at 50 % also.
But, with 32 processors in four chips and a realaxed frequency spec, it would be possible. No need to do 128 decisions simultaneously.
Gunnar Englund
www.gke.org
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100 % recycled posting: Electrons, ideas, finger-tips have been used over and over again...
RE: oscillator bank
But doesn't it take some small number of lines of code to implement this simple function? And that would limit the rate at which one could toggle an output bit?
You and I are clearly on the same page except for the technology implemation.
RE: oscillator bank
I haven't checked new arrivals. There may be more competent ones among them.
Gunnar Englund
www.gke.org
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100 % recycled posting: Electrons, ideas, finger-tips have been used over and over again...
RE: oscillator bank
RE: oscillator bank
Dan - Owner

http://www.Hi-TecDesigns.com
RE: oscillator bank
Keith Cress
Flamin Systems, Inc.- http://www.flaminsystems.com
RE: oscillator bank
Gunnar Englund
www.gke.org
--------------------------------------
100 % recycled posting: Electrons, ideas, finger-tips have been used over and over again...
RE: oscillator bank
If you do simple mixing, then you end up with both plus and minus mixing products. By using a balanced mixer you can select which one you want and reduce the requirement for filtering. You need I & Q phases (90 degrees) to make it work. In a digital processor this might be easy. But I've never even thought about doing balanced modulators in digital as opposed to analog, so I dunno.
But the concept is one of those great 'break glass in case of emergency' ideas. If the other approaches aren't practical, then this one WILL make it work. But it might be something you would only do if absolutely required because of all the extra circuitry.
RE: oscillator bank
Benta.
RE: oscillator bank
My 2nd post in this thread mentioned "If...", but that was intended to compare and contrast (i.e. if). Another post half-way along mentioned 128 BNC output jacks.
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0.01% seemed like a loose frequency requirement, but because of the short time slice required I see now it doesn't permit some of the simpler approaches.
A big, dumb loop still appeals to me a lot because I can simulate it and calculate the tradeoffs in software. But unless I'm mistaken, the access time needed is too fast to use a PROM directly. So the circuit gets complex, with fast RAM and whatever support that needs, and a boot state that loads the RAM from ROM. Sounds like I'm starting to build a computer, which means I could probably find an existing one to use for cheaper.
Calculating what one of the PIC systems, especially a parallel one, can do, is going to be harder. This is a promising solution which warrants a lot more research on my part, so thanks for those pointers.
I really want heterodyning to be useful, but I see some problems. One is that the base frequencies are not multiples of a fixed timer interval, they are linearly spaced frequencies in Hz which makes the intervals logarithmically related. So that's a bit tricky. The other is that with square waves you get the sums and differences of all the spectral components. I think you need to have sine waves for carriers if this is going to work.
Cascaded counters on programmable logic is a very cool solution. It has the nice advantage of being easily scalable once I get something working. Another advantage is that my prototype can be largely the same as my finished product. I have to research what it takes to get started with FPGAs, and what kind of circuitry I would need to support the chip and drive the outputs.
Itsmoked steps back a pace: "skelmonsta; Is there no other way to skin this cat?? This scheme does not sound very elegant. Often that means others are doing it some 'better' way." A reasonable suggestion since I've left out the elegant part of my solution. A commodity audio interface will be used to send the sum of all the carriers to a PC where they are decoded in software. So I get 128 channels of analog data to the computer for cheap. The frequencies of the FFT bins are also usable directly for capacitive sensing over short distances to a common antenna. So once I make my oscillator bank, it's both a sensor and multiplexer. (a floor wax *and* a dessert topping!)
RE: oscillator bank
I guess this goes back to the 128 separate channels...
By the way, there are many modern data communications methods that rely on having 'a zillion' parallel carriers. ADSL, BPL (damn them), I think BlueTooth, and probably many more. It might be worth seeing how they create so many closely-spaced carriers. The USPTO might be able to help.
RE: oscillator bank
RE: oscillator bank
Dan - Owner

http://www.Hi-TecDesigns.com
RE: oscillator bank
The application: imagine a carrier signal in the kHz applied to one antenna a couple of mm from a receiver antenna. The two form a capacitor, and so signal strength in the receiver is inversely proportional to the distance between the pair. I need to get a 2D "image" of the deformation of one surface with respect to a fixed one a couple of mm away into a computer. So, I make the fixed surface a plane antenna and put the carriers over it on the deformable surface. The sum of the carriers contains all of the position measurements as one audio signal that can be decoded on the computer.
Cost is definitely a factor. I would like this to be a sort of cottage industry project or a kit of which there might conceivably be at least hundreds. So, using these carriers to both do the measurement and modulate the data seems like an elegant solution.
RE: oscillator bank
Dan - Owner

http://www.Hi-TecDesigns.com
RE: oscillator bank
Other concepts:
Just switch ONE signal between the 128 output antennas at a rate fast enough to track the (assumed to be slow) physical motion. Switching is easy. There are even 'binary search' tricks using banks of half, quarter, eighth, all the way down, instead of a linear one-by-one approach.
Or perhaps launch acoustic waves across the surface to modulate the distance so that a single parameter will reveal in time the 2-D position.
Or use an optical technique. Holography for example is excruciatingly sensitive. Or laser scanning which is very cost effective these days using cheap bar code hardware.
But perhaps this concept is new and worth trying.
RE: oscillator bank
Any oscillator bank solution will need to source a whole bunch of current when a lot of oscillators are positive simultaneously. This won't happen very often, but when it does, we would like the machine not to break. Roughly 1A total is my back-of-the-envelope result--- what would people add to an FPGA or PIC to do this? Are Darlington arrays appropriate here?
Thanks VE1BLL for all the other suggestions. I have investigated many of these technologies, and others have built some of them, but they tend to have bandwidth limitations. Switching might be part of the answer, but in general this requires synchronization with the FFT step. I was really hoping to keep all of the smarts in the computer.
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You could also collect a large numbere of samples (you have not said how big the FFT array would be) before doing the FFT. This increase the frequency resolution. What this would do for you is that if the subcarriers are not exactly on the center frequencies you want (but you know what they are) the FFT will bin these frequencies correctly but with a reduced but exactly known amplitude reduction. So you could correct for this.
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Regards